Example #1
0
def bus(address, write, modules):
    control_lines = []
    for prefix, size, data_in in modules:
        prefix //= 2**size
        control_lines.append(equals(prefix, address[size:]))
    data_out = word_switch(control_lines, *[d for p, s, d in modules])
    write_lines = [And(write, ctrl) for ctrl in control_lines]
    return data_out, write_lines
Example #2
0
def test_jmp2():
    """ same deal as above but with automatic signals so more realistic timing """
    network = Network()
    clock = Switch(network)
    data_in = BinaryIn(network, 8)
    pc_in = PlaceholderWord(network, 8)
    write_pc = Placeholder(network)

    def step():
        network.drain()
        clock.write(True)
        network.drain()
        clock.write(False)
        network.drain()

    addr, data_out, write = cpu_core(clock, data_in, pc_in, write_pc)
    write_pc = write_pc.replace(And(write, mux.equals(102, addr)))
    pc_in = pc_in.replace(data_out)

    addr = BinaryOut(addr)
    data_out = BinaryOut(data_out)

    # fetch addr1 from pc
    network.drain()
    assert not write.read()
    assert addr.read() == 0
    data_in.write(100)

    # fetch data from addr1
    step()
    assert not write.read()
    assert addr.read() == 100
    data_in.write(200)

    # fetch addr2 from pc
    step()
    assert not write.read()
    assert addr.read() == 1
    data_in.write(102)

    # write data to addr2 AND PC
    step()
    assert write.read()
    assert addr.read() == 102
    assert data_out.read() == 200

    # fetch addr1 from pc
    step()
    assert not write.read()
    assert addr.read() == 200
    data_in.write(99)

    # fetch data from addr1
    step()
    assert not write.read()
    assert addr.read() == 99
    data_in.write(98)

    # fetch addr2 from pc
    step()
    assert not write.read()
    assert addr.read() == 201
    data_in.write(97)

    # write data to addr2
    step()
    assert write.read()
    assert addr.read() == 97
    assert data_out.read() == 98