from scipy.sparse import coo_matrix
def printn(*args, **kwargs):
for i in args:
sys.stdout.write(str(i))
gnucap.command("set trace")
gnucap.command("set lang=acs")
## Set gnucap run mode
runmode = gnucap.SET_RUN_MODE(gnucap.rBATCH)
gnucap.command("set lang=spice")
gnucap.parse("Vin 1 0 dc 0 ac 1.0")
gnucap.parse("R1 1 2 1e3")
gnucap.parse("R2 1 3 1e3")
gnucap.parse("C2 1 4 1")
gnucap.parse("R2 2 4 1e3")
gnucap.parse("L2 3 5 1m")
gnucap.parse("C1 2 0 1e-8")
gnucap.command("list")
class MyAC(gnucap.SIM):
def do_it(self, cmd, scope):
self._scope = scope
self._sim.set_command_ac()
self._sim.init()
def port_name(self, x):
return ["P", "N"][x]
def value_name(self):
return "incomplete"
s = myvs()
# s._y[0] not yet. how to do that?
s._y[0]
print("mtest", s.max_nodes(), s.long_label())
s2 = s.clone()
print("mtest", s2.max_nodes(), s2.long_label())
# s.clone()
print("TT", type(s))
a = install_device("myvs", s)
# b = gnucap.command_installer("myvs", s)
gnucap.command("set lang=verilog")
gnucap.parse("resistor #(.r(1)) r(1 0)")
# gnucap.parse("vsource #(.dc(1)) s(1 0)")
gnucap.parse("myvs #() s(1 0)")
gnucap.command("list")
gnucap.command("print dc fourtytwo(s) i(r) v(s) nodeprobe(s) v(nodes)")
gnucap.command("dc r 1 3 .5")
print("done")
# testing environment override
import os
os.environ["GNUCAP_LANG"] = "verilog"
import gnucap
gnucap.parse("resistor r1(0,1)")
gnucap.command("list")
gnucap.parse("error_1")
gnucap.command("error_2") # TODO: can't see any error
# Copyright (C) 2018 Felix Salfelder
# Author: Felix Salfelder <*****@*****.**>
from __future__ import print_function
import gnucap
gnucap.command("set lang spice")
gnucap.parse("V1 1 0 ac 1")
gnucap.command("set lang verilog")
gnucap.parse("capacitor #(.c(1u)) c(1 nout)")
gnucap.parse("resistor #(.r(1k)) s(nout 0)")
gnucap.command("store ac v(nout)")
gnucap.command("ac 1 1024 * 4")
w = gnucap.CKT_BASE_find_wave("v(nout)")
b = iter(w)
for i in range(6):
n = next(b)
print(n[0], ' {:.6e}'.format(n[1]))
try:
next(b)
assert (False)
except StopIteration:
pass
for i in w:
def tr_iwant_matrix(self):
pass
def tr_probe_num(self, s):
return 4.
# uses default if not specified.
# def clone(self):
# return __class__(self)
d4 = mytype4()
b2 = install_device("mytype4", d4)
command("set lang verilog")
parse("dummy #() d();")
parse("mytype #() a1();")
parse("mytype4 #() a4(0, 0);")
parse("resistor #() r(0,0);")
cl = CARD_LIST().card_list_()
for a in cl:
print(a.long_label(), a.dev_type())
import sys
sys.stdout.flush()
command("list")
command("print op test(*)")
command("op")
# (C) 2018 Felix Salfelder
# GPLv3
#
# this is part of gnucap-python
import gnucap, os, sys
from gnucap import command, parse
f=open("crash.sp", "w")
f.write("spice\n")
f.write(".subckt a 1 2 3\n")
f.write("r1 1 2 3\n")
f.write(".ends\n")
f.close()
command("get crash.sp")
os.remove("crash.sp")
parse("X1 1 3 4 a")
command("list")
print("end of crashtest")
return 0;
def port_number(self):
return 2
def port_name(self,x):
return ["P","N"][x]
def value_name(self):
return "incomplete"
s = somecomponent()
print("mtest", s.max_nodes(), s.long_label())
s2 = s.clone()
# s2.tr_begin()
print("mtest", s2.max_nodes(), s2.long_label())
# s.clone()
print("TT", type(s))
a = install_device("somecomp", s)
# b = gnucap.command_installer("somecomp2", s)
gnucap.command("set lang=verilog")
gnucap.parse("vsource #(.dc(1)) v(1 0)")
gnucap.parse("somecomp #() s(1 0)")
gnucap.command("list")
gnucap.command("print dc fourtytwo(s) v(s)")
gnucap.command("dc v 0 1 .5")
gnucap.command("print transient fourtytwo(s) v(s)")
gnucap.command("transient 0 1 .5")
print("done")
def custom(self):
return 42
def clone(self):
print("somelt clone")
x = mytype(self)
self.HACK.append(x)
x.__class__ = mytype
return x
s = mytype()
d1 = install_device("mytype", s)
command("set lang verilog")
parse("mytype #() a();")
parse("resistor #() r(0,0);")
cl = CARD_LIST().card_list_()
print("tst")
for a in cl:
print(a.long_label(), "..")
if(isinstance(a, mytype)):
print(".. is mytype")
assert(42==a.custom())
assert(isinstance(a, ELEMENT))
if(isinstance(a, ELEMENT)):
print(".. is element")
assert(isinstance(a, COMPONENT))
ELEMENT.__init__(self)
else:
ELEMENT.__init__(self, other)
def custom(self):
return 42
def dev_type(self):
return "mytype0"
def clone(self):
s = mytype(self)
return s
m = mytype()
a = install("mytype0|y", m)
b = install("y", m)
command("set lang verilog")
parse("mytype0 #() a0();")
parse("mytype1 #() a1();")
parse("mytype2 #() a2();")
parse("resistor #() r(0,0);")
cl = CARD_LIST().card_list_()
for a in cl:
print(a.long_label(), a.dev_type())
command("simcmd")
# inspired by "custom_ac.py" 2009-2011 Henrik Johansson
from __future__ import print_function
import os
import numpy as np
import gnucap
gnucap.command("set trace")
gnucap.command("set lang=acs")
## Set gnucap run mode
runmode = gnucap.SET_RUN_MODE(gnucap.rBATCH)
gnucap.command("set lang=spice")
gnucap.parse("Vin 1 0 dc 0 ac 1.0")
gnucap.parse("R1 1 2 1e3")
gnucap.parse("C1 2 0 1e-8")
gnucap.command("list")
class MyAC(gnucap.SIM):
def do_it(self, cmd, scope):
self._scope = scope
self._sim.set_command_ac()
self._sim.init()
self._sim.alloc_vectors()
acx = self._sim._acx
acx.reallocate()
def net_nodes(self):
return 2
def max_nodes(self):
return 2
def ac_iwant_matrix(self):
pass
def tr_iwant_matrix(self):
pass
def tr_probe_num(self, s):
return 4.
# uses default if not specified.
# def clone(self):
# return __class__(self)
command("set lang verilog")
parse("mytype2 #() a2();")
parse("mytype3 #() a3();")
parse("mytype4 #() a4(0, 0);")
cl = CARD_LIST().card_list_()
for a in cl:
print(a.long_label(), a.dev_type())
import sys
sys.stdout.flush()
command("list")
command("print op test(*)")
command("op")