def test():
data = {
'project_file': it.PROJECT_FILE,
'path': p.join(VIM_HDL_EXAMPLES, 'another_library', 'foo.vhd'),
'content': '-- TODO: Nothing to see here'
}
ui_reply = it.app.post('/get_ui_messages', data)
reply = it.app.post('/get_messages_by_path', data)
_logger.info("UI reply: %s", ui_reply)
_logger.info("Reply: %s", reply)
messages = reply.json['messages']
for message in messages:
it.assertTrue(utils.samefile(message.pop('filename'),
data['path']))
it.assertIn(
{
"error_type": "W",
"checker": "HDL Code Checker/static",
"line_number": 1,
"column": 4,
"error_subtype": "",
"error_number": "0",
"error_message": "TODO: Nothing to see here"
}, messages)
def test():
if it.BUILDER_NAME not in ('msim', 'ghdl', 'xvhdl'):
_logger.info("Test requires a builder")
return
source = VhdlParser(
p.join(it.SOURCES_PATH, 'source_with_error.vhd'))
records, rebuilds = it.builder.build(source, forced=True)
for record in records:
_logger.info(record)
if it.BUILDER_NAME == 'msim':
expected = [{
'line_number': '4',
'error_number': '1136',
'error_message': 'Unknown identifier "some_lib".',
'column': None,
'error_type': 'E',
'checker': 'msim'
}]
elif it.BUILDER_NAME == 'ghdl':
expected = [{
'line_number': '4',
'error_number': None,
'error_message': 'no declaration for "some_lib"',
'column': '5',
'error_type': 'E',
'checker': 'ghdl'
}]
elif it.BUILDER_NAME == 'xvhdl':
expected = [{
'line_number': '4',
'error_number': 'VRFC 10-91',
'error_message': 'some_lib is not declared',
'column': None,
'error_type': 'E',
'checker': 'xvhdl'
}]
it.assertEqual(len(records), 1)
it.assertTrue(
utils.samefile(records[0].pop('filename'), source.filename))
it.assertEquals(records, expected)
it.assertEqual(rebuilds, [])
def test005b():
filename = p.join(VIM_HDL_EXAMPLES, 'another_library', 'foo.vhd')
original_content = open(filename, 'r').read().split('\n')
content = '\n'.join(original_content[:43] +
['signal another_signal : std_logic;'] +
original_content[43:])
it.assertTrue(it.project._msg_queue.empty())
records = it.project.getMessagesWithText(filename, content)
_logger.debug("Records received:")
for record in records:
_logger.debug("- %s", record)
else:
_logger.warning("No records found")
# Check that all records point to the original filename and
# remove them from the records so it's easier to compare
# the remaining fields
for record in records:
record_filename = record.pop('filename')
if record_filename:
it.assertTrue(samefile(filename, record_filename))
it.assertItemsEqual([{
'error_subtype': 'Style',
'line_number': 43,
'checker': 'HDL Code Checker/static',
'error_message': "signal 'neat_signal' is never used",
'column': 12,
'error_type': 'W',
'error_number': '0'
}, {
'error_subtype': 'Style',
'line_number': 44,
'checker': 'HDL Code Checker/static',
'error_message': "signal 'another_signal' is never used",
'column': 8,
'error_type': 'W',
'error_number': '0'
}], records)
it.assertTrue(it.project._msg_queue.empty())
def test():
if it.BUILDER_NAME not in ('msim', 'ghdl', 'xvhdl'):
_logger.info("Test requires a builder")
return
source = VhdlParser(p.join(it.SOURCES_PATH,
'source_with_error.vhd'))
records, rebuilds = it.builder.build(source, forced=True)
for record in records:
_logger.info(record)
if it.BUILDER_NAME == 'msim':
expected = [{
'line_number': '4',
'error_number': '1136',
'error_message': 'Unknown identifier "some_lib".',
'column': None,
'error_type': 'E',
'checker': 'msim'}]
elif it.BUILDER_NAME == 'ghdl':
expected = [{
'line_number': '4',
'error_number': None,
'error_message': 'no declaration for "some_lib"',
'column': '5',
'error_type': 'E',
'checker': 'ghdl'}]
elif it.BUILDER_NAME == 'xvhdl':
expected = [{
'line_number': '4',
'error_number': 'VRFC 10-91',
'error_message': 'some_lib is not declared',
'column': None,
'error_type': 'E',
'checker': 'xvhdl'}]
it.assertEqual(len(records), 1)
it.assertTrue(utils.samefile(records[0].pop('filename'),
source.filename))
it.assertEquals(records, expected)
it.assertEqual(rebuilds, [])
def test007():
if not it.PROJECT_FILE:
_logger.info("Requires a valid project file")
return
filename = p.join(VIM_HDL_EXAMPLES, 'basic_library',
'clock_divider.vhd')
it.assertTrue(it.project._msg_queue.empty())
records = []
for record in it.project.getMessagesByPath(filename):
it.assertTrue(samefile(filename, record.pop('filename')))
records += [record]
if it.BUILDER_NAME == 'msim':
expected_records = [{
'checker':
'msim',
'column':
None,
'error_message':
"Synthesis Warning: Reset signal 'reset' "
"is not in the sensitivity list of process "
"'line__58'.",
'error_number':
None,
'error_type':
'W',
'line_number':
'58'
}]
elif it.BUILDER_NAME == 'ghdl':
expected_records = []
elif it.BUILDER_NAME == 'xvhdl':
expected_records = []
it.assertEquals(records, expected_records)
it.assertTrue(it.project._msg_queue.empty())
def test005c():
filename = 'some_file.vhd'
writeListToFile(filename, [
"entity some_entity is end;",
])
content = "\n".join([
"library work;", "use work.all;", "entity some_entity is end;"
])
it.assertTrue(it.project._msg_queue.empty())
records = it.project.getMessagesWithText(filename, content)
_logger.debug("Records received:")
for record in records:
_logger.debug("- %s", record)
# Check that all records point to the original filename and
# remove them from the records so it's easier to compare
# the remaining fields
for record in records:
record_filename = record.pop('filename')
if record_filename:
it.assertTrue(samefile(filename, record_filename))
if it.project.builder.builder_name in ('msim', 'ghdl', 'xvhdl'):
it.assertItemsEqual([{
'error_type': 'W',
'checker': 'HDL Code Checker/static',
'error_message':
"Declaration of library 'work' can be omitted",
'column': 9,
'error_subtype': 'Style',
'error_number': '0',
'line_number': 1
}, {
'error_type':
'W',
'checker':
'hdlcc',
'error_message':
'Path "%s" not found in project file' %
p.abspath(filename),
'column':
'',
'error_number':
'',
'line_number':
''
}], records)
else:
it.assertItemsEqual([{
'error_type': 'W',
'checker': 'HDL Code Checker/static',
'error_message':
"Declaration of library 'work' can be omitted",
'column': 9,
'error_subtype': 'Style',
'error_number': '0',
'line_number': 1
}], records)
it.assertTrue(it.project._msg_queue.empty())