def _impl(self):
# prepare constants and bit arrays for inputs
DW = int(self.DATA_WIDTH)
polyBits, PW = CrcComb.parsePoly(self.POLY, self.POLY_WIDTH)
XOROUT = int(self.XOROUT)
finBits = [hBit(selectBit(XOROUT, i))
for i in range(PW)]
# rename "dataIn_data" to "d" to make code shorter
_d = self.wrapWithName(self.dataIn.data, "d")
inBits = list(iterBits(_d))
if not self.IN_IS_BIGENDIAN:
inBits = reversedEndianity(inBits)
state = self._reg("c",
Bits(self.POLY_WIDTH),
self.INIT)
stateBits = list(iterBits(state))
# build xor tree for CRC computation
crcMatrix = CrcComb.buildCrcXorMatrix(DW, polyBits)
res = CrcComb.applyCrcXorMatrix(
crcMatrix, inBits,
stateBits, bool(self.REFIN))
# next state logic
# wrap crc next signals to separate signal to have nice code
stateNext = []
for i, crcbit in enumerate(res):
b = self.wrapWithName(crcbit, "crc_%d" % i)
stateNext.append(b)
If(self.dataIn.vld,
# regNext is in format 0 ... N, we need to reverse it to litle
# endian
state(Concat(*reversed(stateNext)))
)
# output connection
if self.REFOUT:
finBits = reversed(finBits)
self.dataOut(
Concat(*[rb ^ fb
for rb, fb in zip(iterBits(state), finBits)]
)
)
else:
self.dataOut(state ^ Concat(*finBits))
def build_crc_xor_matrix(self,
state_in_bits: List[RtlSignal],
poly_bits: List[int], data_in_bits:[RtlSignal])\
->List[RtlSignal]:
"""
build xor tree for CRC computation
"""
crcMatrix = CrcComb.buildCrcXorMatrix(len(data_in_bits), poly_bits)
res = CrcComb.applyCrcXorMatrix(crcMatrix, data_in_bits, state_in_bits,
self.REFIN)
# next state logic
# wrap crc next signals to separate signal to have nice code
stateNext = []
for i, crcbit in enumerate(res):
b = rename_signal(self, crcbit, f"crc_{i:d}")
stateNext.append(b)
return stateNext
def _impl(self):
# prepare constants and bit arrays for inputs
DW = int(self.DATA_WIDTH)
polyBits, PW = CrcComb.parsePoly(self.POLY, self.POLY_WIDTH)
XOROUT = int(self.XOROUT)
finBits = [hBit(selectBit(XOROUT, i)) for i in range(PW)]
# rename "dataIn_data" to "d" to make code shorter
_d = self.wrapWithName(self.dataIn.data, "d")
inBits = list(iterBits(_d))
if not self.IN_IS_BIGENDIAN:
inBits = reversedEndianity(inBits)
state = self._reg("c", Bits(self.POLY_WIDTH), self.INIT)
stateBits = list(iterBits(state))
# build xor tree for CRC computation
crcMatrix = CrcComb.buildCrcXorMatrix(DW, polyBits)
res = CrcComb.applyCrcXorMatrix(crcMatrix, inBits, stateBits,
bool(self.REFIN))
# next state logic
# wrap crc next signals to separate signal to have nice code
stateNext = []
for i, crcbit in enumerate(res):
b = self.wrapWithName(crcbit, "crc_%d" % i)
stateNext.append(b)
If(
self.dataIn.vld,
# regNext is in format 0 ... N, we need to reverse it to litle
# endian
state(Concat(*reversed(stateNext))))
# output connection
if self.REFOUT:
finBits = reversed(finBits)
self.dataOut(
Concat(*[rb ^ fb for rb, fb in zip(iterBits(state), finBits)]))
else:
self.dataOut(state ^ Concat(*finBits))