def _impl(self):
# prepare constants and bit arrays for inputs
DW = int(self.DATA_WIDTH)
polyBits, PW = CrcComb.parsePoly(self.POLY, self.POLY_WIDTH)
XOROUT = int(self.XOROUT)
finBits = [hBit(selectBit(XOROUT, i))
for i in range(PW)]
# rename "dataIn_data" to "d" to make code shorter
_d = self.wrapWithName(self.dataIn.data, "d")
inBits = list(iterBits(_d))
if not self.IN_IS_BIGENDIAN:
inBits = reversedEndianity(inBits)
state = self._reg("c",
Bits(self.POLY_WIDTH),
self.INIT)
stateBits = list(iterBits(state))
# build xor tree for CRC computation
crcMatrix = CrcComb.buildCrcXorMatrix(DW, polyBits)
res = CrcComb.applyCrcXorMatrix(
crcMatrix, inBits,
stateBits, bool(self.REFIN))
# next state logic
# wrap crc next signals to separate signal to have nice code
stateNext = []
for i, crcbit in enumerate(res):
b = self.wrapWithName(crcbit, "crc_%d" % i)
stateNext.append(b)
If(self.dataIn.vld,
# regNext is in format 0 ... N, we need to reverse it to litle
# endian
state(Concat(*reversed(stateNext)))
)
# output connection
if self.REFOUT:
finBits = reversed(finBits)
self.dataOut(
Concat(*[rb ^ fb
for rb, fb in zip(iterBits(state), finBits)]
)
)
else:
self.dataOut(state ^ Concat(*finBits))
def _impl(self):
# prepare constants and bit arrays for inputs
DW = int(self.DATA_WIDTH)
polyBits, PW = CrcComb.parsePoly(self.POLY, self.POLY_WIDTH)
XOROUT = int(self.XOROUT)
finBits = [hBit(selectBit(XOROUT, i)) for i in range(PW)]
# rename "dataIn_data" to "d" to make code shorter
_d = self.wrapWithName(self.dataIn.data, "d")
inBits = list(iterBits(_d))
if not self.IN_IS_BIGENDIAN:
inBits = reversedEndianity(inBits)
state = self._reg("c", Bits(self.POLY_WIDTH), self.INIT)
stateBits = list(iterBits(state))
# build xor tree for CRC computation
crcMatrix = CrcComb.buildCrcXorMatrix(DW, polyBits)
res = CrcComb.applyCrcXorMatrix(crcMatrix, inBits, stateBits,
bool(self.REFIN))
# next state logic
# wrap crc next signals to separate signal to have nice code
stateNext = []
for i, crcbit in enumerate(res):
b = self.wrapWithName(crcbit, "crc_%d" % i)
stateNext.append(b)
If(
self.dataIn.vld,
# regNext is in format 0 ... N, we need to reverse it to litle
# endian
state(Concat(*reversed(stateNext))))
# output connection
if self.REFOUT:
finBits = reversed(finBits)
self.dataOut(
Concat(*[rb ^ fb for rb, fb in zip(iterBits(state), finBits)]))
else:
self.dataOut(state ^ Concat(*finBits))
def _impl(self):
# prepare constants and bit arrays for inputs
poly_bits, PW = CrcComb.parsePoly(self.POLY, self.POLY_WIDTH)
din = self.dataIn
# rename "dataIn_data" to "d" to make code shorter
_d = rename_signal(self, din.data, "d")
data_in_bits = list(iterBits(_d))
if not self.IN_IS_BIGENDIAN:
data_in_bits = bit_list_reversed_endianity(data_in_bits)
if self.MASK_GRANULARITY:
din.rd(1)
rst = self.rst_n._isOn() | (din.vld & din.last)
else:
rst = self.rst_n
state = self._reg("c", Bits(self.POLY_WIDTH), self.INIT, rst=rst)
state_in_bits = list(iterBits(state))
if self.MASK_GRANULARITY is None or self.MASK_GRANULARITY == self.DATA_WIDTH:
state_next = self.build_crc_xor_matrix(state_in_bits, poly_bits,
data_in_bits)
If(
din.vld,
# state_next is in format 0 ... N,
# we need to reverse it to litle-endian
state(Concat(*reversed(state_next))))
else:
mask_in = din.mask
mask_width = mask_in._dtype.bit_length()
state_next_cases = []
for vld_byte_cnt in range(1, mask_width + 1):
# because bytes are already reversed in bit vector of input bits
_data_in_bits = data_in_bits[(mask_width - vld_byte_cnt) *
self.MASK_GRANULARITY:]
state_next = self.build_crc_xor_matrix(state_in_bits,
poly_bits,
_data_in_bits)
# reversed because of because of MSB..LSB
state_next_cases.append(
(mask(vld_byte_cnt), state(Concat(*reversed(state_next)))))
If(
din.vld,
Switch(mask_in).add_cases(state_next_cases).Default(
state(None)))
# output connection
if self.LATENCY == 0:
state = state.next
elif self.LATENCY == 1:
if self.MASK_GRANULARITY is not None:
# to avoid the case where the state is restarted by dataIn.last
state_tmp = self._reg("state_tmp", state._dtype)
state_tmp(state.next)
state = state_tmp
else:
raise NotImplementedError(self.LATENCY)
XOROUT = int(self.XOROUT)
fin_bits = [BIT.from_py(get_bit(XOROUT, i)) for i in range(PW)]
fin_bits = rename_signal(self, Concat(*fin_bits), "fin_bits")
if self.REFOUT:
state_reversed = rename_signal(self, Concat(*iterBits(state)),
"state_revered")
state = state_reversed
self.dataOut(state ^ fin_bits)