def main(): parser = argparse.ArgumentParser( description="Build test file for dummy or eptri module") builder_args(parser) soc_core_args(parser) parser.add_argument('--dir', metavar='DIRECTORY', default='build', help='Output directory (defauilt: %(default)s)') parser.add_argument('--csr', metavar='CSR', default='csr.csv', help='csr file (default: %(default)s)') parser.add_argument("--rom-init", default=None, help="rom_init file") args = parser.parse_args() soc_kwargs = soc_core_argdict(args) if args.rom_init is not None: soc_kwargs["integrated_rom_init"] = \ get_mem_data(args.rom_init, endianness='little') output_dir = args.dir platform = Platform() soc = BaseSoC(platform, **soc_kwargs) builder = Builder(soc, output_dir=output_dir, csr_csv=args.csr, compile_software=False) vns = builder.build(run=False) soc.do_exit(vns) print("""Simulation build complete. Output files: {}/gateware/dut.v Source Verilog file. Run this under Cocotb. """.format(output_dir))
def main(): parser = argparse.ArgumentParser( description="Build Fomu Main Gateware") parser.add_argument( "--seed", default=0, help="seed to use in nextpnr" ) parser.add_argument( "--placer", default="heap", choices=["sa", "heap"], help="which placer to use in nextpnr" ) parser.add_argument( "--no-pll", help="disable pll -- this is easier to route, but may not work", action="store_true" ) parser.add_argument( "--board", choices=["evt", "pvt", "hacker"], required=True, help="build for a particular hardware board" ) args = parser.parse_args() if args.board == "pvt": from litex_boards.partner.platforms.fomu_pvt import Platform elif args.board == "hacker": from litex_boards.partner.platforms.fomu_hacker import Platform elif args.board == "evt": from litex_boards.partner.platforms.fomu_evt import Platform platform = Platform() soc = BaseSoC(platform, pnr_seed=args.seed, placer=args.placer, use_pll=not args.no_pll) builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv", compile_software=False) vns = builder.build() soc.do_exit(vns)
def main(): parser = argparse.ArgumentParser( description="Build Fomu Main Gateware") parser.add_argument( "--seed", default=0, help="seed to use in nextpnr" ) parser.add_argument( "--placer", default="heap", choices=["sa", "heap"], help="which placer to use in nextpnr" ) parser.add_argument( "--board", choices=["evt", "pvt", "hacker"], required=True, help="build for a particular hardware board" ) args = parser.parse_args() soc = BaseSoC(args.board, pnr_seed=args.seed, pnr_placer=args.placer, usb_bridge=True) # Add the LED driver block. Get the `rgb_led` pins from the definition # file, then instantiate the module we defined above. led_pads = soc.platform.request("rgb_led") soc.submodules.fomu_rgb = FomuRGB(led_pads) # Indicate that `fomu_rgb` is a CSR, and should be added to the bus. # Otherwise we wouldn't be able to access `fomu_rgb` at all. # Note that the value here must match the value above, so if you did # `soc.submodules.frgb = FomuRGB(led_pads)` then you would need to # change this to `soc.add_csr("frgb")`. soc.add_csr("fomu_rgb") builder = Builder(soc, output_dir="build", csr_csv="build/csr.csv", compile_software=False) vns = builder.build() soc.do_exit(vns) add_dfu_suffix(os.path.join('build', 'gateware', 'fomu_{}.bin'.format(args.board)))
def main(): parser = argparse.ArgumentParser( description="Build Xoulon Development SoC Gateware") parser.add_argument("--seed", default=0, help="seed to use in nextpnr") parser.add_argument( "--document-only", default=False, action="store_true", help="Don't build gateware or software, only build documentation") args = parser.parse_args() soc = XoulonSoC("evt", cpu_type="vexriscv", cpu_variant="min+debug", usb_bridge=True, pnr_seed=args.seed) builder = Builder(soc, output_dir="build", csr_csv="build/csr.csv", compile_software=False, compile_gateware=not args.document_only) vns = builder.build() soc.do_exit(vns) lxsocdoc.generate_docs(soc, "build/documentation/", project_name="Xoulon Test MCU", author="Sean \"xobs\" Cross") lxsocdoc.generate_svd(soc, "build/software", vendor="Foosn", name="Xoulon")
def main(): if 'sim' in argv: dut = DUT() generators = { "sys": [main_generator(dut)], "eth_tx": [dut.ethphy.phy_sink.generator(), dut.ethphy.generator()], "eth_rx": dut.ethphy.phy_source.generator() } clocks = {"sys": 10, "eth_rx": 10, "eth_tx": 10} run_simulation(dut, generators, clocks, vcd_name="udp_sender.vcd") return soc = DevSoC() soc.platform.name = 'hello_10G' builder = Builder( soc, compile_gateware='synth' in argv, csr_csv='./build/csr.csv', csr_json='./build/csr.json', ) if ('build' in argv) or ('synth' in argv): vns = builder.build() soc.analyzer.do_exit(vns) if 'load' in argv: prog = soc.platform.create_programmer() prog.load_bitstream( join(builder.gateware_dir, soc.platform.name + ".bit"))
def main(): parser = argparse.ArgumentParser( description="Build test file for dummy or eptri module") parser.add_argument('--dir', metavar='DIRECTORY', default='build', help='Output directory (default: %(default)s)') parser.add_argument('--csr', metavar='CSR', default='csr.csv', help='csr file (default: %(default)s)') args = parser.parse_args() output_dir = args.dir platform = Platform() soc = BaseSoC(platform, cpu_type=None, cpu_variant=None, output_dir=output_dir) builder = Builder(soc, output_dir=output_dir, csr_csv=args.csr, compile_software=False) vns = builder.build(run=False) soc.do_exit(vns) print("""Simulation build complete. Output files: {}/gateware/dut.v Source Verilog file. Run this under Cocotb. """.format(output_dir))
def main(): parser = argparse.ArgumentParser(description="Build Fomu Main Gateware") parser.add_argument("--seed", default=0, help="seed to use in nextpnr") parser.add_argument("--placer", default="heap", choices=["sa", "heap"], help="which placer to use in nextpnr") parser.add_argument("--board", choices=["evt", "pvt", "hacker"], required=True, help="build for a particular hardware board") args = parser.parse_args() soc = BaseSoC(args.board, pnr_seed=args.seed, pnr_placer=args.placer, usb_bridge=True) builder = Builder(soc, output_dir="build", csr_csv="build/csr.csv", compile_software=False) vns = builder.build() soc.do_exit(vns) add_dfu_suffix(os.path.join('build', 'gateware', 'top.bin'))
def main(): parser = argparse.ArgumentParser(description="Build the Hack a Day Supercon 2019 Badge firmware") parser.add_argument( "-D", "--document-only", action="store_true", help="don't build software or gateware, only build documentation", ) parser.add_argument( "--sim", help="generate files for simulation", action="store_true" ) args = parser.parse_args() compile_gateware = True compile_software = True if args.sim: compile_gateware = False compile_software = False platform = CocotbPlatform() CocotbPlatform.add_fsm_state_names() else: platform = BadgePlatform() if args.document_only: compile_gateware = False compile_software = False soc = BaseSoC(platform, is_sim=args.sim) builder = Builder(soc, output_dir="build", csr_csv="build/csr.csv", compile_software=compile_software, compile_gateware=compile_gateware) vns = builder.build() soc.do_exit(vns) lxsocdoc.generate_docs(soc, "build/documentation", project_name="Hack a Day Supercon 2019 Badge", author="Sean \"xobs\" Cross")
def main(): parser = argparse.ArgumentParser( description="SDRAM Loopback SoC on Marble*") builder_args(parser) soc_core_args(parser) parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") parser.add_argument("--ethernet-phy", default="rgmii", help="select Ethernet PHY (rgmii or 1000basex)") parser.add_argument("-p", "--program-only", action="store_true", help="Don't build, just program the existing bitfile") parser.add_argument("--build", action="store_true", help="Build FPGA bitstream") parser.add_argument("--load", action="store_true", help="program FPGA") args = parser.parse_args() if args.build: soc = SDRAMLoopbackSoC(with_ethernet=args.with_ethernet, **soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) # discard result, or save in vns? builder.build(run=not args.program_only) if args.load: prog = kc705.Platform().create_programmer() prog.load_bitstream( os.path.join("build", "kc705", "gateware", "kc705.bit"))
def main(): parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker") parser.add_argument("--sys-clk-freq", type=float, default=48e6, help="Select system clock frequency") parser.add_argument("--document-only", action="store_true", help="Do not build a soc. Only generate documentation.") parser.add_argument("--flash", action="store_true", help="Load bitstream") builder_args(parser) soc_core_args(parser) args = parser.parse_args() # Create the SOC soc = BaseSoC(sys_clk_freq=int(args.sys_clk_freq), **soc_core_argdict(args)) # Configure command line parameter defaults # Don't build software -- we don't include it since we just jump to SPI flash. builder_kwargs = builder_argdict(args) builder_kwargs["compile_software"] = False if args.document_only: builder_kwargs["compile_gateware"] = False if builder_kwargs["csr_svd"] is None: builder_kwargs["csr_svd"] = "../litex-pac/soc.svd" # Create and run the builder builder = Builder(soc, **builder_kwargs) builder.build() # If requested load the resulting bitstream onto the iCEBreaker if args.flash: IceStormProgrammer().flash(0x00000000, "build/icebreaker/gateware/icebreaker.bin")
def main(): parser = argparse.ArgumentParser(description="LiteX SoC on MarbleMini") builder_args(parser) soc_sdram_args(parser) # soc_core_args(parser) parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") parser.add_argument("--ethernet-phy", default="rgmii", help="select Ethernet PHY (rgmii or 1000basex)") parser.add_argument("-p", "--program-only", action="store_true", help="select Ethernet PHY (rgmii or 1000basex)") args = parser.parse_args() if args.with_ethernet: soc = LTCSocDev(phy=args.ethernet_phy, **soc_sdram_argdict(args)) # soc = EthernetSoC(phy=args.ethernet_phy, **soc_sdram_argdict(args)) # soc = EthernetSoC(phy=args.ethernet_phy, **soc_core_argdict(args)) else: soc = BaseSoC(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) if not args.program_only: vns = builder.build() if False: soc.analyzer.do_exit(vns) prog = soc.platform.create_programmer() import os prog.load_bitstream(os.path.join(builder.gateware_dir, "marblemini.bit"))
def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Leech") parser.add_argument("--sys-clk-freq", type=float, default=48e6, help="Select system clock frequency") parser.add_argument( "--document-only", action="store_true", help="Do not build a soc. Only generate documentation.") builder_args(parser) soc_core_args(parser) args = parser.parse_args() # Create the SOC soc = BaseSoC(sys_clk_freq=int(args.sys_clk_freq), **soc_core_argdict(args)) # Configure command line parameter defaults # Don't build software: we don't have CPU. builder_kwargs = builder_argdict(args) builder_kwargs["compile_software"] = False if args.document_only: builder_kwargs["compile_gateware"] = False if builder_kwargs["csr_svd"] is None: builder_kwargs["csr_svd"] = "../litex-pac/soc.svd" # Create and run the builder builder = Builder(soc, **builder_kwargs) builder.build()
def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Arty") builder_args(parser) soc_core_args(parser) args = parser.parse_args() cls = BaseSoC soc = cls(**soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build()
def main(): description = "Linux on LiteX-VexRiscv\n\n" description += "Available boards:\n" for name in supported_boards.keys(): description += "- " + name + "\n" parser = argparse.ArgumentParser( description=description, formatter_class=argparse.RawTextHelpFormatter) parser.add_argument("--board", required=True, help="FPGA board") parser.add_argument("--build", action="store_true", help="build bitstream") parser.add_argument("--load", action="store_true", help="load bitstream (to SRAM)") parser.add_argument("--flash", action="store_true", help="flash bitstream/images (to SPI Flash)") parser.add_argument("--local-ip", default="192.168.1.50", help="local IP address") parser.add_argument("--remote-ip", default="192.168.1.100", help="remote IP address of TFTP server") args = parser.parse_args() if args.board == "all": board_names = list(supported_boards.keys()) else: board_names = [args.board] for board_name in board_names: board = supported_boards[board_name]() soc_kwargs = {} if board_name in ["versa_ecp5", "ulx3s"]: soc_kwargs["toolchain"] = "trellis" soc_kwargs["cpu_variant"] = "linux+no-dsp" soc = SoCLinux(board.soc_cls, **soc_kwargs) if "spiflash" in board.soc_capabilities: soc.add_spi_flash() soc.add_constant("SPIFLASH_PAGE_SIZE", board.SPIFLASH_PAGE_SIZE) soc.add_constant("SPIFLASH_SECTOR_SIZE", board.SPIFLASH_SECTOR_SIZE) if "ethernet" in board.soc_capabilities: soc.configure_ethernet(local_ip=args.local_ip, remote_ip=args.remote_ip) soc.configure_boot() soc.compile_device_tree(board_name) if args.build: builder = Builder(soc, output_dir="build/" + board_name) builder.build() if args.load: board.load() if args.flash: board.flash()
def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Arty") builder_args(parser) soc_sdram_args(parser) vivado_build_args(parser) args = parser.parse_args() cls = MinSoC soc = cls(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build(**vivado_build_argdict(args))
def main(): parser = argparse.ArgumentParser(description="LiteX SoC on TinyFPGA_BX") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--seed", default=0, help="Seed to use in Nextpnr") parser.add_argument("--placer", default="heap", choices=["sa", "heap"], help="Which placer to use in Nextpnr") builder_args(parser) soc_core_args(parser) args = parser.parse_args() soc = BaseSoC(pnr_placer=args.placer, pnr_seed=args.seed, debug=True, **soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build)
def generate(output_dir, csr_csv): platform = Platform() soc = BaseSoC(platform, cpu_type=None, cpu_variant=None, output_dir=output_dir) builder = Builder(soc, output_dir=output_dir, csr_csv=csr_csv, compile_software=False) vns = builder.build(run=False, build_name="dut") soc.do_exit(vns)
def main(): parser = argparse.ArgumentParser(description="Datapipe simulation SoC*") builder_args(parser) soc_core_args(parser) # soc_core_args(parser) parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") parser.add_argument("--ethernet-phy", default="rgmii", help="select Ethernet PHY (rgmii or 1000basex)") parser.add_argument("-p", "--program-only", action="store_true", help="Don't build, just program the existing bitfile") parser.add_argument("--build", action="store_true", help="Build FPGA bitstream") parser.add_argument("--load", action="store_true", help="program FPGA") parser.add_argument("--threads", default=4, help="set number of threads (default=4)") parser.add_argument("--trace", action="store_true", help="enable VCD tracing") args = parser.parse_args() soc_kwargs = soc_core_argdict(args) sim_config = SimConfig(default_clk="sys_clk") soc_kwargs["integrated_main_ram_size"] = 0x10000 soc_kwargs = soc_core_argdict(args) soc_kwargs["uart_name"] = "sim" # sim_config.add_module("serial2console", "serial") sim_config.add_module('ethernet', "eth", args={ "interface": "xxx1", "ip": "192.168.88.101", "vcd_name": "foo.vcd" }) soc = SDRAMSimSoC(phy="rgmii", with_ethernet=True, with_etherbone=True, with_sdram=True, etherbone_ip_address="192.168.88.50", etherbone_mac_address=0x12345678abcd, **soc_kwargs) builder = Builder(soc, **builder_argdict(args)) # discard result, or save in vns? builder.build(threads=args.threads, trace=args.trace, sim_config=sim_config)
def main(): parser = argparse.ArgumentParser(description="Arty LiteX SoC") builder_args(parser) parser.add_argument("--nocompile-gateware", action="store_true") args = parser.parse_args() platform = arty.Platform() soc = EtherboneSoC(platform) builder = Builder(soc, output_dir="build", compile_gateware=not args.nocompile_gateware, csr_csv="test/csr.csv") vns = builder.build()
def main(): parser = argparse.ArgumentParser( description="Minimal Arty DDR3 Design for tests with Project X-Ray" ) parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") args = parser.parse_args() if args.load: load() soc = BaseSoC() builder = Builder(soc, output_dir="build", csr_csv="csr.csv") builder.build(run=args.build) soc.generate_sdram_phy_py_header()
def main(): parser = argparse.ArgumentParser( formatter_class=argparse.RawTextHelpFormatter) parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream (to SRAM)") VexRiscvSMP.args_fill(parser) args = parser.parse_args() # build bootrom subprocess.check_call("make", cwd="bootrom") # CPU parameters --------------------------------------------------------------------------- # Do memory accesses through Wishbone and L2 cache when L2 size is configured. args.with_wishbone_memory = True VexRiscvSMP.args_read(args) # SoC creation ----------------------------------------------------------------------------- soc_kwargs = { "integrated_sram_size": 0x0, "integrated_rom_size": 0x400, "l2_size": 0x4000, # Use Wishbone and L2 for memory accesses. "with_uart": False, } rom_data = get_mem_data("bootrom/rom.bin", endianness="little", mem_size=soc_kwargs["integrated_rom_size"]) soc_kwargs["integrated_rom_init"] = rom_data soc = De0SoC(**soc_kwargs) board_name = "de0nano" # Build ------------------------------------------------------------------------------------ build_dir = os.path.join("build", board_name) builder = Builder(soc, csr_json=os.path.join(build_dir, "csr.json"), csr_csv=os.path.join(build_dir, "csr.csv"), compile_software=False) builder.build(run=args.build) # DTS -------------------------------------------------------------------------------------- generate_dts(board_name) compile_dts(board_name) # Load FPGA bitstream ---------------------------------------------------------------------- if args.load: prog = soc.platform.create_programmer() prog.load_bitstream( os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
def main(): parser = argparse.ArgumentParser(description="SDRAM Loopback SoC on Marble*") builder_args(parser) soc_core_args(parser) parser.add_argument("--ip", default="192.168.19.70", help="Assign an ip address") parser.add_argument("--ethernet-phy", default="rgmii", help="select Ethernet PHY (rgmii or 1000basex)") parser.add_argument("-p", "--program-only", action="store_true", help="Don't build, just program the existing bitfile") parser.add_argument("--build", action="store_true", help="Build FPGA bitstream") parser.add_argument("--load", action="store_true", help="program FPGA") parser.add_argument("--threads", default=4, help="set number of threads (default=4)") parser.add_argument("--trace", action="store_true", help="enable VCD tracing") parser.add_argument("-s", "--sim", action="store_true", help="Simulate") args = parser.parse_args() if args.sim: soc_kwargs = soc_core_argdict(args) sim_config = SimConfig(default_clk="sys_clk") soc_kwargs["integrated_main_ram_size"] = 0x10000 soc_kwargs = soc_core_argdict(args) soc_kwargs["uart_name"] = "sim" # sim_config.add_module("serial2console", "serial") sim_config.add_module( 'ethernet', "eth", args={"interface": "xxx1", "ip": "192.168.88.101", "vcd_name": "foo.vcd"}) soc = SDRAMSimSoC(phy="rgmii", with_ethernet=True, with_etherbone=True, with_sdram=True, etherbone_ip_address="192.168.88.50", etherbone_mac_address=0x12345678abcd, **soc_kwargs) builder = Builder(soc, **builder_argdict(args)) # discard result, or save in vns? builder.build( threads=args.threads, trace=args.trace, sim_config=sim_config) kwargs = soc_core_argdict(args) # soc = SDRAMLoopbackSoC(ip=args.ip, phy=args.ethernet_phy, **kwargs) soc = SDRAMDevSoC(ip=args.ip, phy=args.ethernet_phy, **kwargs) builder = Builder(soc, **builder_argdict(args)) builder.build() if args.load: prog = marble.Platform().create_programmer() prog.load_bitstream(os.path.join("build", "marble", "gateware", "marble.bit"))
def main(): parser = common.ArgumentParser( description="LiteX SoC on DDR4 Datacenter Test Board", sys_clk_freq='50e6', module='MTA18ASF2G72PZ') g = parser.add_argument_group(title="DDR4 Datacenter Test Board") parser.add(g, "--eth-reset-time", default="10e-3", help="Duration of Ethernet PHY reset") parser.add(g, "--iodelay-clk-freq", default="200e6", help="IODELAY clock frequency") vivado_build_args(g) args = parser.parse_args() soc_kwargs = common.get_soc_kwargs(args) soc = SoC(**soc_kwargs) target_name = 'ddr4_datacenter_test_board' builder_kwargs = common.get_builder_kwargs(args, target_name=target_name) builder = Builder(soc, **builder_kwargs) build_kwargs = vivado_build_argdict(args) if not args.sim else {} common.run(args, builder, build_kwargs, target_name=target_name)
def main(): parser = common.ArgumentParser( description="LiteX SoC on Arty A7", sys_clk_freq='100e6', module='MT41K128M16', ) g = parser.add_argument_group(title="Arty A7") parser.add(g, "--toolchain", default="vivado", choices=['vivado', 'symbiflow'], help="Gateware toolchain to use") parser.add(g, "--variant", default="a7-35", choices=['a7-35', 'a7-100'], help="FPGA variant") vivado_build_args(g) args = parser.parse_args() soc_kwargs = common.get_soc_kwargs(args) soc = SoC(variant=args.variant, toolchain=args.toolchain, **soc_kwargs) target_name = 'arty' builder_kwargs = common.get_builder_kwargs(args, target_name=target_name) builder = Builder(soc, **builder_kwargs) build_kwargs = vivado_build_argdict(args) if not args.sim else {} common.run(args, builder, build_kwargs, target_name=target_name)
def main(): cpu_type = "vexriscv" cpu_variant = "linux+debug" if False: cpu_type = None cpu_variant = None platform = BadgePlatform() soc = BaseSoC(platform, is_sim=False, debug=True, cpu_type=cpu_type, cpu_variant=cpu_variant, csr_address_width=16, sao0_disable=True, sao1_disable=True, genio_disable=True, ) sao0_pwmgroup = PWMGroup(soc, "sao0", platform.request("sao", 0)) sao1_pwmgroup = PWMGroup(soc, "sao1", platform.request("sao", 1)) platform.add_extension(pmod_cubed) soc.submodules.pmod2 = GPIOBidirectional(platform.request("pmod2")) soc.add_csr("pmod2") soc.submodules.pmod3 = GPIOBidirectional(platform.request("pmod3")) soc.add_csr("pmod3") soc.submodules.pmod4 = GPIOBidirectional(platform.request("pmod4")) soc.add_csr("pmod4") builder = Builder(soc, output_dir="build", csr_csv="csr.csv", compile_software=True, compile_gateware=True) for package in builder.software_packages: if package[0] == "bios": builder.software_packages.remove(package) break builder.add_software_package("bios", src_dir="../../../sw") vns = builder.build() soc.do_exit(vns) lxsocdoc.generate_docs(soc, builder.output_dir + "/documentation", project_name="Hack a Day Supercon 2019 Badge", author="was Sean \"xobs\" Cross")
def main(): parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker") parser.add_argument("--flash-offset", default=0x40000, help="Boot offset in SPI Flash") parser.add_argument("--sys-clk-freq", type=float, default=21e6, help="Select system clock frequency") parser.add_argument( "--document-only", action="store_true", help="Do not build a soc. Only generate documentation.") parser.add_argument("--flash", action="store_true", help="Load bitstream") builder_args(parser) soc_core_args(parser) args = parser.parse_args() # Create the SOC soc = BaseSoC(flash_offset=args.flash_offset, sys_clk_freq=int(args.sys_clk_freq), **soc_core_argdict(args)) # Configure command line parameter defaults # Don't build software -- we don't include it since we just jump to SPI flash. builder_kwargs = builder_argdict(args) builder_kwargs["compile_software"] = False if args.document_only: builder_kwargs["compile_gateware"] = False if builder_kwargs["csr_svd"] is None: builder_kwargs["csr_svd"] = "../litex-pac/soc.svd" if builder_kwargs["memory_x"] is None: builder_kwargs["memory_x"] = "../litex-pac/memory.x" # Create and run the builder builder = Builder(soc, **builder_kwargs) builder.build() lxsocdoc.generate_docs(soc, "build/documentation/", project_name="iCEBreaker LiteX RISC-V Example SOC", author="Piotr Esden-Tempski") # If requested load the resulting bitstream onto the iCEBreaker if args.flash: prog = soc.platform.create_programmer() prog.flash(0x00000000, "build/icebreaker/gateware/icebreaker.bin")
def generate_verilog(): platform = LatticePlatform("", io=[], toolchain="diamond") platform.add_extension(gen._io) core_config = { "clk_freq": int(125e6), "phy": liteeth_phys.LiteEthECP5PHYRGMII, "mac_address": 0xAA040000CFCF, "ip_address": "192.168.178.50", "port": 1710, } soc = gen.UDPCore(platform, core_config) with tempfile.TemporaryDirectory() as tmpdirname: builder = Builder(soc, compile_gateware=False, output_dir=tmpdirname) builder.build(build_name="liteeth_core") return (Path(tmpdirname) / "gateware" / "liteeth_core.v").read_bytes()
def main(): parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker") parser.add_argument("--seed", default=0, help="seed to use in nextpnr") parser.add_argument("--placer", default="heap", choices=["sa", "heap"], help="which placer to use in nextpnr") parser.add_argument("--cpu", action="store_true", help="Add a CPU to the build") parser.add_argument( "--debug", action="store_true", help="Add debug features. UART has to be used with the wishbone-tool.") builder_args(parser) soc_core_args(parser) args = parser.parse_args() kwargs = builder_argdict(args) print(kwargs) if args.cpu: kwargs["cpu_type"] = "vexriscv" kwargs["cpu_variant"] = "min" soc = BaseSoC(pnr_placer=args.placer, pnr_seed=args.seed, debug=args.debug, **kwargs) kwargs = builder_argdict(args) # Don't build software -- we don't include it since we just jump # to SPI flash. kwargs["compile_software"] = False builder = Builder(soc, **kwargs) vns = builder.build() soc.do_exit(vns) lxsocdoc.generate_docs(soc, "build/documentation/", project_name="iCEBreaker LiteX Riscv Example SOC", author="Piotr Esden-Tempski")
def main(): parser = argparse.ArgumentParser( description=__doc__, formatter_class=argparse.RawTextHelpFormatter) parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") parser.add_argument("--with-rts-reset", action="store_true", help="Connect UART RTS line to sys_clk reset") parser.add_argument("--with-bist", action="store_true", help="Add DDR3 BIST Generator/Checker") parser.add_argument( "--spd-dump", type=str, help= "DDR3 configuration file, dumped using the `spdread` command in LiteX BIOS" ) builder_args(parser) soc_core_args(parser) args = parser.parse_args() soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone, with_bist=args.with_bist, spd_dump=args.spd_dump, **soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) if args.load: prog = soc.platform.create_programmer() prog.load_bitstream( os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main(): """Entry point""" args = parse_args() soc = ZephyrSoC(sys_clk_freq=SYS_CLK_FREQ, output_dir=OUTPUT_DIR) builder = Builder( soc, output_dir=OUTPUT_DIR, csr_svd=os.path.join(OUTPUT_DIR, "csr.svd"), csr_csv=os.path.join(OUTPUT_DIR, "csr.csv"), ) builder.build(run=args.build) if args.load: prog = soc.platform.create_programmer() prog.cable_name = "Arrow-USB-Blaster" # Programmer used on board prog.load_bitstream( os.path.join(builder.gateware_dir, soc.build_name + ".sof"))