def main():
cpu_type = "vexriscv"
cpu_variant = "linux+debug"
if False:
cpu_type = None
cpu_variant = None
platform = BadgePlatform()
soc = BaseSoC(platform,
is_sim=False,
debug=True,
cpu_type=cpu_type,
cpu_variant=cpu_variant,
csr_address_width=16,
sao0_disable=True,
sao1_disable=True,
genio_disable=True,
)
sao0_pwmgroup = PWMGroup(soc, "sao0", platform.request("sao", 0))
sao1_pwmgroup = PWMGroup(soc, "sao1", platform.request("sao", 1))
platform.add_extension(pmod_cubed)
soc.submodules.pmod2 = GPIOBidirectional(platform.request("pmod2"))
soc.add_csr("pmod2")
soc.submodules.pmod3 = GPIOBidirectional(platform.request("pmod3"))
soc.add_csr("pmod3")
soc.submodules.pmod4 = GPIOBidirectional(platform.request("pmod4"))
soc.add_csr("pmod4")
builder = Builder(soc,
output_dir="build",
csr_csv="csr.csv",
compile_software=True,
compile_gateware=True)
for package in builder.software_packages:
if package[0] == "bios":
builder.software_packages.remove(package)
break
builder.add_software_package("bios", src_dir="../../../sw")
vns = builder.build()
soc.do_exit(vns)
lxsocdoc.generate_docs(soc,
builder.output_dir + "/documentation",
project_name="Hack a Day Supercon 2019 Badge", author="was Sean \"xobs\" Cross")
def main():
soc_cls = BaseSoC
cpu = VexRiscv
parser = argparse.ArgumentParser(description="LiteX SoC")
builder_args(parser)
soc_core_args(parser)
parser.add_argument("--build_gateware", action='store_true')
parser.add_argument("--yosys", action="store_true")
parser.add_argument("--sim", action="store_true")
parser.add_argument("--run", action="store_true")
args = parser.parse_args()
builder_kwargs = builder_argdict(args)
soc_kwargs = soc_core_argdict(args)
platform = sim_platform2.Platform() if args.sim else platform1.Platform()
output_dir = builder_kwargs['output_dir'] = 'build'
fw_file = os.path.join(output_dir, "software", "firmware", "firmware.bin")
soc_kwargs['integrated_rom_size'] = 32 * 1024
soc_kwargs["integrated_main_ram_size"] = 16 * 1024
try:
soc_kwargs['integrated_main_ram_init'] = get_mem_data(
fw_file, cpu.endianness)
except OSError:
pass
soc = BaseSoC(platform,
cpu=cpu,
sim=args.sim,
output_dir=output_dir,
**soc_kwargs)
builder = Builder(soc, **builder_kwargs)
builder.add_software_package("firmware",
src_dir=os.path.join(os.getcwd(), 'src',
'firmware'))
if args.sim:
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
builder.build(run=False, sim_config=sim_config, opt_level='O3')
if args.run:
builder.build(build=False, sim_config=sim_config)
else:
builder.build(run=args.build_gateware,
synth_mode="yosys" if args.yosys else "vivado")
def main():
description = "Linux on LiteX-VexRiscv\n\n"
description += "Available boards:\n"
for name in supported_boards.keys():
description += "- " + name + "\n"
parser = argparse.ArgumentParser(description=description, formatter_class=argparse.RawTextHelpFormatter)
parser.add_argument("--board", required=True, help="FPGA board")
parser.add_argument("--build", action="store_true", help="build bitstream")
parser.add_argument("--build_sw", action="store_true", help="build software only")
parser.add_argument("--load", action="store_true", help="load bitstream (to SRAM)")
parser.add_argument("--flash", action="store_true", help="flash bitstream/images (to SPI Flash)")
parser.add_argument("--flash_gw", action="store_true", help="flash bitstream/images (to SPI Flash)")
parser.add_argument("--flash_bios", action="store_true", help="flash bios (to SPI Flash)")
parser.add_argument("--flash_fw", action="store_true", help="flash firmware (to SPI Flash)")
parser.add_argument("--local-ip", default="192.168.1.50", help="local IP address")
parser.add_argument("--remote-ip", default="192.168.1.100", help="remote IP address of TFTP server")
args = parser.parse_args()
if args.board == "all":
board_names = list(supported_boards.keys())
else:
board_names = [args.board]
for board_name in board_names:
board = supported_boards[board_name]()
soc_kwargs = {}
if board_name in ["versa_ecp5", "ulx3s"]:
soc_kwargs["toolchain"] = "trellis"
if board_name in ["qmatech"]:
soc = SoCVexRiscv(board.soc_cls, **soc_kwargs)
elif board_name in ["ae4gx"]:
soc = SoCAE4GX(board.soc_cls, **soc_kwargs)
elif board_name in ["basys3"]:
soc = SoCBASYS3(board.soc_cls, **soc_kwargs)
elif board_name in ["at7core"]:
soc = SoCAT7CORE(board.soc_cls, **soc_kwargs)
elif board_name in ["ice40_hx8k_b_evn"]:
soc = SoCICE40HX(board.soc_cls, **soc_kwargs)
elif board_name in ["ice40_up5k_b_evn"]:
soc = SoCICE40UP(board.soc_cls, **soc_kwargs)
else:
soc = SoCLinux(board.soc_cls, **soc_kwargs)
if args.build:
builder = Builder(soc, output_dir="build/" + board_name)
builder.add_software_package(name="firmware")
builder.build()
if args.build_sw:
builder = Builder(soc, output_dir="build/" + board_name, compile_gateware=False)
builder.add_software_package(name="firmware")
builder.build()
if args.load:
board.load()
if args.flash:
board.flash_gw()
board.flash_bios()
board.flash_fw()
if args.flash_gw:
board.flash_gw()
if args.flash_bios:
board.flash_bios()
if args.flash_fw:
board.flash_fw()
