def tbstim():
yield delay(10)
print("{0:<8d} ".format(now()))
yield delay(1000)
print("{0:<8d} ".format(now()))
for _ in range(10):
yield delay(1000)
def mon_state():
print(" :{:<8d}: initial state {}".format(now(), str(state)))
while True:
yield state
print(" :{:<8d}: state transition --> {}".format(
now(), str(state)))
def consumer(q):
yield delay(100)
while 1:
print("%s: TRY to get item" % now())
yield q.get()
print("%s: GOT item %s" % (now(), q.item))
yield delay(30)
def bench(self):
clk = Signal(0)
sig1 = Signal(0)
sig2 = Signal(0)
td = 10
def gen(s, n):
for i in range(n-1):
yield delay(td)
s.next = 1
yield delay(td)
for i in range(10):
offset = now()
n0 = randrange(1, 50)
n1 = randrange(1, 50)
n2 = randrange(1, 50)
sig1.next = 0
sig2.next = 0
yield join(delay(n0*td), gen(sig1, n1), gen(sig2, n2))
assert sig1.val == 1
assert sig2.val == 1
assert now() == offset + td * max(n0, n1, n2)
raise StopSimulation("Joined concurrent generator yield")
def bench(self):
clk = Signal(0)
sig1 = Signal(0)
sig2 = Signal(0)
td = 10
def gen(s, n):
s.next = 0
for i in range(n):
yield delay(td)
s.next = 1
for i in range(100):
offset = now()
n1 = randrange(2, 10)
n2 = randrange(n1+1, 20) # n2 > n1
yield delay(td), gen(sig1, n1), gen(sig2, n2)
assert sig1.val == 0
assert sig2.val == 0
assert now() == offset + td
yield sig1.posedge
assert sig2.val == 0
assert now() == offset + n1*td
yield sig2.posedge
assert now() == offset + n2*td
raise StopSimulation("Concurrent generator yield")
def tbstim():
yield delay(10)
print("{0:<8d} ".format(now()))
yield delay(1000)
print("{0:<8d} ".format(now()))
for _ in range(10):
yield delay(1000)
def bench(self):
clk = Signal(0)
sig1 = Signal(0)
sig2 = Signal(0)
td = 10
def gen(s, n):
s.next = 0
for i in range(n):
yield delay(td)
s.next = 1
for i in range(100):
offset = now()
n1 = randrange(2, 10)
n2 = randrange(n1+1, 20) # n2 > n1
yield delay(0), gen(sig1, n1), gen(sig2, n2)
self.assertEqual(sig1.val, 0)
self.assertEqual(sig2.val, 0)
self.assertEqual(now(), offset + 0)
yield sig1.posedge
self.assertEqual(sig2.val, 0)
self.assertEqual(now(), offset + n1*td)
yield sig2.posedge
self.assertEqual(now(), offset + n2*td)
raise StopSimulation, "Zero delay yield"
def bench(self):
clk = Signal(0)
sig1 = Signal(0)
sig2 = Signal(0)
td = 10
def gen(s, n):
for i in range(n-1):
yield delay(td)
s.next = 1
yield delay(td)
for i in range(10):
offset = now()
n0 = randrange(1, 50)
n1 = randrange(1, 50)
n2 = randrange(1, 50)
sig1.next = 0
sig2.next = 0
yield join(delay(n0*td), gen(sig1, n1), gen(sig2, n2))
self.assertEqual(sig1.val, 1)
self.assertEqual(sig2.val, 1)
self.assertEqual(now(), offset + td * max(n0, n1, n2))
raise StopSimulation, "Joined concurrent generator yield"
def toHost_check():
"""
Wait for a write to toHost register.
"""
if toHost != 1:
raise Error('Test failed. MTOHOST = {0}. Time = {1}'.format(toHost, now()))
print("Time: {0}".format(now()))
raise StopSimulation
def tbstim():
print("[{:8d}] 1a: ".format(hdl.now()), x, y, yy)
yield hdl.delay(10)
yield clock.posedge
yield clock.posedge
print("[{:8d}] 2a: ".format(hdl.now()), x, y, yy)
assert yy == 7
raise hdl.StopSimulation
def mon_state():
print(" :{:<8d}: initial state {}".format(
now(), str(state)))
while True:
yield state
print(" :{:<8d}: state transition --> {}".format(
now(), str(state)))
def test():
for i in range(0, 100, 2):
self.assertEquals(now(), i*half_period)
yield clk.posedge
self.assertEquals(now(), (i+1)*half_period)
yield clk.negedge
raise StopSimulation()
def toHost_check():
"""
Wait for a write to toHost register.
"""
if toHost != 1:
raise Error('Test failed. MTOHOST = {0}. Time = {1}'.format(
toHost, now()))
print("Time: {0}".format(now()))
raise StopSimulation
def tb_monitor():
if SLWR or SLRD or SLOE or FLAGA or FLAGB or FLAGC or FLAGD:
fm.trace_print(' %d control signal changed' % (now()))
if ADDR == 0:
fm.trace_print(' %d address is zero' % (now()))
else:
fm.trace_print(' %d address not zero %d' % (now(), ADDR))
if FDI != FDO:
fm.trace_print(' %d data input != output' % (now()))
def timeout():
rst.next = True
yield hdl.delay(RESET_TIME * TICK_PERIOD)
rst.next = False
yield hdl.delay(TIMEOUT * TICK_PERIOD)
raise hdl.Error(
"Test failed: TIMEOUT at {0}. Clock cycles: {1}".format(
hdl.now(),
hdl.now() // TICK_PERIOD))
def tb_monitor():
if SLWR or SLRD or SLOE or FLAGA or FLAGB or FLAGC or FLAGD:
fm.trace_print(' %d control signal changed' % (now()))
if ADDR == 0:
fm.trace_print(' %d address is zero' % (now()))
else:
fm.trace_print(' %d address not zero %d' % (now(), ADDR))
if FDI != FDO:
fm.trace_print(' %d data input != output' % (now()))
def receive_data_process():
global recv_data,nb2
if (src_bfm_o.valid_o == 1):
nb2+=1
#print str(nb2) + ". Received data from sink bfm:", ": ", src_bfm_o.data_o
recv_data.append(int(src_bfm_o.data_o))
sim_time_now=now()
if (nb2 == MAX_NB_TRANSFERS):
raise StopSimulation("Simulation Finished in %d clks: In total " %now() + str(MAX_NB_TRANSFERS) + " data words received")
def spin():
if cnt == 4 - 1:
toggle.next = not toggle
cnt.next = 0
print("%s triple tick" %
now()) #triggered at 3.5 clock cyles --> 70 ns
else:
cnt.next = cnt + 1
print("%s tick" % now())
def receive_data_process():
TIME_SHUTDOWN = 5000
nb_recv = 0
sim_time_now = now()
nb_recv += nb_receive
if (nb_recv == (MAX_NB_TRANSFERS)):
print("INF242: Num ready pulses: " + str(int(ready_pulses)))
raise StopSimulation("Simulation Finished in %d clks: In total " %
now() + str(nb_recv) + " data words received")
def tbstim():
print("[{:8d}] 1b: ".format(hdl.now()), a, b, c)
a.next = 2
b.next = 4
yield hdl.delay(10)
for ii in range(6):
print("[{:8d}] {}b: ".format(hdl.now(), ii), a, b, c)
yield clock.posedge
assert c == 7
raise hdl.StopSimulation
def receive_data_process():
TIME_SHUTDOWN=5000
nb_recv=0
sim_time_now=now()
for i in range(NB_CHAIN_MULTIPLIERS):
nb_recv+=nb_receive[i]
if(nb_recv == NB_CHAIN_MULTIPLIERS* (MAX_NB_TRANSFERS)):
for i in range(NB_CHAIN_MULTIPLIERS):
print("INF242: mult: " +str(i)+ " Num ready pulses: "+ str(int(ready_pulses[i])))
raise StopSimulation("Simulation Finished in %d clks: In total " %now() + str(nb_recv) + " data words received")
def stimulus():
a = Signal(0)
yield delay(10)
a.next = 1
yield None, delay(10)
assert a.val == 0
assert now() == 10
yield delay(0)
assert a.val == 1
assert now() == 10
def stimulus():
a = Signal(0)
yield delay(10)
a.next = 1
yield None, delay(10)
self.assertEqual(a.val, 0)
self.assertEqual(now(), 10)
yield delay(0)
self.assertEqual(a.val, 1)
self.assertEqual(now(), 10)
def tb_reset():
while True:
print('%8d ... Wait Reset' % (now()))
yield self.doreset.posedge
print('%8d ... Do Reset' % (now()))
fx.RST.next = False
yield delay(13*self.IFCLK_TICK)
fx.RST.next = True
yield delay(13*self.IFCLK_TICK)
self.doreset.next = False
print('%8d ... End Reset' % (now()))
def tb_reset():
while True:
print('%8d ... Wait Reset' % (now()))
yield self.doreset.posedge
print('%8d ... Do Reset' % (now()))
fx.RST.next = False
yield delay(13 * self.IFCLK_TICK)
fx.RST.next = True
yield delay(13 * self.IFCLK_TICK)
self.doreset.next = False
print('%8d ... End Reset' % (now()))
def computePL1():
done.next = state_done
if not state_go: # state_go
state_done.next = False # state_done
stage_m.next = False # stage_mp
sig_l1c.next = 0
for i in range(r_l1m): sig_l1m[i] = 0
conv_cord_x.next = 0
conv_cord_y.next = 0
patch_x.next = 0
patch_y.next = 0
patch_cumu.next = False
if go:
state_go.next = True
if __debug__:
print " now %s good state start" % now()
else:
if not state_done: # state_done
if not stage_m: # stage_mp
if __debug__:
print " now %s stage p x %u y %u p %u %u" % (
now(), conv_cord_x, conv_cord_y,
patch_x, patch_y)
if not patch_cumu:
fltidx = patch_x + patch_y * p
pixidx = (conv_cord_x + patch_x) + (conv_cord_y + patch_y) * p
sig_l1c.next = sig_l1c + filter[fltidx] * pixels[pixidx]
if patch_x >= p-1 and patch_y >= p-1:
patch_cumu.next = True
elif patch_x >= p-1:
patch_x.next = 0
patch_y.next = patch_y + 1
else:
patch_x.next = patch_x + 1
else:
pixidx = conv_cord_x + conv_cord_y * p
mid1c[pixidx] = sig_l1c[16:8]
patch_cumu.next = False
patch_x.next = 0
patch_y.next = 0
if conv_cord_x >= n_l1c - 1 and conv_cord_y >= n_l1c - 1:
stage_m.next = True
elif conv_cord_x == n_l1c - 1:
conv_cord_x.next = 0
conv_cord_y.next = conv_cord_y + 1
else:
conv_cord_x.next = conv_cord_x + 1
else:
if __debug__:
print " now %s stage m x %u y %u p %u %u" % (
now(), conv_cord_x, conv_cord_y,
patch_x, patch_y)
state_done.next = True
def tbstim():
yield clkwait(hostintf.clk, count=20)
yield hostintf.writeconfig(0x340, 0x00000002)
yield mdiointf.mdc.posedge
time_mdc = now()
yield mdiointf.mdc.posedge
time_mdc = now() - time_mdc
yield hostintf.clk.posedge
time_hostclk = now()
yield hostintf.clk.posedge
time_hostclk = now() - time_hostclk
assert time_hostclk == time_mdc / 6
def _wait_data(self, ep, num=1, timeout=100):
ok = False
to = timeout * 1e6
te = now() + to
for ii in range(timeout):
if self.isdata(ep, num=num):
ok = True
break
time.sleep(1)
if now() > te:
break
return ok
def _wait_empty(self, ep, timeout=100):
ok = False
to = timeout * 1e6
te = now() + to
for ii in range(timeout):
if self.isempty(ep):
ok = True
break
time.sleep(1)
if now() > te:
break
return ok
def light_deposit_things():
for count, i in enumerate(time):
if (now() == i):
outputs[count].next = amplitudes[count]
else:
outputs[count].next = Signal(intbv(0)[8:])
if ((i - now()) > 0):
line = self.w.find_withtag("ASIC{}_line".format(count))
y_value = (200 * (count + 1))
x_value = 700 + ((i - now()) / 5)
coord = (x_value, y_value, x_value + 50, y_value)
self.w.coords(line, coord)
def tbstim():
resetext.next = not resetext.active
yield delay(33 * ticks_per_ns)
for ii in range(3):
yield dripple.posedge
ts = myhdl.now()
yield dripple.posedge
td = myhdl.now() - ts
yield delay(100 * ticks_per_ns)
print(td, 2 * ticks_per_ns * 1e3)
# assert td == 2 * ticks_per_ns * 1e3
yield delay(100 * ticks_per_ns)
raise myhdl.StopSimulation
def tbstim():
resetext.next = not resetext.active
yield delay(33*ticks_per_ns)
for ii in range(3):
yield dripple.posedge
ts = myhdl.now()
yield dripple.posedge
td = myhdl.now() - ts
yield delay(100*ticks_per_ns)
print(td, 2*ticks_per_ns*1e3)
# assert td == 2 * ticks_per_ns * 1e3
yield delay(100*ticks_per_ns)
raise myhdl.StopSimulation
def testlogic():
reset.next = 0
yield delay(15)
reset.next = 1
yield delay(20)
print("Converted! %d" % now())
raise StopSimulation
def monitor():
yield self.rx_ready.posedge, delay(500000)
yield delay(1)
print(now())
self.assertEquals(self.rx_msg, 0x0FFFFFFFFFFF)
self.assertTrue(self.rx_ready)
self.stop_simulation()
def datacheck():
protocol_ref = tbm_ref.ipcore_ref.get_protocol_ref()
mydest = tbm_ref.ipcore_ref.get_address()
check_data = tbm_ref.checkvect
while True:
# just check for data reception
yield din
# check packet
inpacket = din.val
# search checkvect by data payload
chkidx = check_dict.get(inpacket["data"])
if chkidx is None:
tbm_ref.error(
"sourcechkgen.datacheck: unexpected packet : %s" %
repr(inpacket))
else:
# check vectors : (<time from src>, <src>, <value>)
expected_vector = check_data[chkidx]
# received packet: report it
received_idx[chkidx] = True
# data was checked before. Inform about packet delay
tbm_ref.debug(
"sourcechkgen.datacheck: (delay %d) packet received : <%s>, expected src=<%s>, value=<%s> "
% (myhdl.now() - expected_vector[0], repr(inpacket),
repr(expected_vector[1]), repr(expected_vector[2])))
if inpacket["src"] != expected_vector[1]:
tbm_ref.error(
"sourcechkgen.datacheck: source address != %d (%d)" %
(expected_vector[1], inpacket["src"]))
if inpacket["dst"] != mydest:
tbm_ref.error(
"sourcechkgen.datacheck: destination address != %d (%d)"
% (mydest, inpacket["dst"]))
def stimulus():
zero = fixbv(0.0, min=fix_min, max=fix_max, res=fix_res)
yield clk.posedge
# random initialization
for j in range(embedding_dim):
word_emb[j].next = fixbv(random.uniform(0.0, emb_spread),
min=fix_min,
max=fix_max,
res=fix_res)
context_emb[j].next = fixbv(random.uniform(0.0, emb_spread),
min=fix_min,
max=fix_max,
res=fix_res)
# iterate to converge
for i in range(n):
yield clk.negedge
print "%4s mse: %f, y: %f, word: %s, context: %s" % (
now(), error, y, [float(el.val) for el in word_emb
], [float(el.val) for el in context_emb])
if error == zero:
break
# transfer new values
for j in range(embedding_dim):
word_emb[j].next = new_word_emb[j]
context_emb[j].next = new_context_emb[j]
raise StopSimulation()
def response(self, clause, expected):
self.assert_(len(expected) > 100) # we should test something
i = 0
while 1:
yield clause
self.assertEqual(now(), expected[i])
i += 1
def debug_internals():
print "-" * 78
print "time %s | clk %i | clk_pc %i | ip %i " % (now(), clk,
clk_pc, ip)
print 'pc_add_o %i | branch_add_o %i | BranchZ %i | next_ip %i' % (
pc_adder_out, branch_adder_out, branchZ, next_ip)
print 'instruction', bin(instruction, 32)
print 'opcode %s | rs %i | rt %i | rd %i | shamt %i | func %i | address %i' % \
(bin(opcode, 6), rs, rt, rd, shamt, func, address)
print 'wr_reg_in %i | dat1 %i | dat2 %i | muxALUo %i ' % \
(wr_reg_in, data1, data2, mux_alu_out)
print 'RegDst %i | ALUSrc %i | Mem2Reg %i | RegW %i | MemR %i | MemW %i | Branch %i | ALUop %s' % (
RegDst, ALUSrc, MemtoReg, RegWrite, MemRead, MemWrite, Branch,
bin(ALUop, 2))
print 'func: %s | aluop: %s | alu_c_out: %s' % (bin(
func, 5), bin(ALUop, 2), bin(alu_control_out, 4))
print 'ALU_out: %i | Zero: %i' % (alu_out, zero)
print 'ram_out %i | mux_ram_out %i ' % (ram_out, mux_ram_out)
def beh_strobe():
#print ("%s posedge!"% now())
# Generate the strobe event, use the "greater
# than" for initial condition cases. Count the
# number of clock ticks that equals the LED strobe rate
if clk_cnt >= cnt_max - 1:
clk_cnt.next = 0
strobe.next = True
else:
clk_cnt.next = clk_cnt + 1
strobe.next = False
# Describe the strobing, note the following always
# changes direction and "resets" when either the lsb
# or msb is set. This handles our initial condition
# as well.
if strobe:
if led_bit_mem[msb]:
led_bit_mem.next = msb_reverse_val
left_not_right.next = False
print("ltr")
elif led_bit_mem[lsb]:
led_bit_mem.next = lsb_reverse_val
left_not_right.next = True
print("rtl")
else:
if left_not_right:
led_bit_mem.next = led_bit_mem << 1
else:
led_bit_mem.next = led_bit_mem >> 1
print("%s moving %s" % (now(), str(led_bit_mem)))
def response(self, clause, expected):
assert len(expected) > 100 # we should test something
i = 0
while 1:
yield clause
assert now() == expected[i]
i += 1
def debug_check():
print("base address {:4X}, max address {:4X}".format(
int(base_address), int(max_address)))
while True:
assert clock is wb.clk_i is self.clock
assert reset is wb.rst_i is self.reset
yield clock.posedge
print(
"{:8d}: c:{}, r:{}, {} {} {} sel:{}, wr:{} n:{} "
"acnt {}, @{:04X}, i:{:02X} o:{:02X} ({:02X})".format(
now(),
int(clock),
int(reset),
int(wb.cyc_i),
int(wb.we_i),
int(wb.ack_o),
int(lwb_sel),
int(lwb_wr),
int(newcyc),
int(ackcnt),
int(wb.adr_i),
int(wb.dat_i),
int(wb.dat_o),
int(lwb_do),
))
def test():
print("t z a b sel")
for i in range(8):
a.next, b.next, sel.next = randrange(8), randrange(8), randrange(2)
yield delay(2)
print("%d %s %s %s %s" % (now(), z, a, b, sel))
def testNegedge(self):
""" Negedge waveform test """
s = self.sig
stimulus = self.stimulus()
expected = getExpectedTimes(self.waveform, isNegedge)
response = self.response(clause=s.negedge, expected=expected)
self.runSim(Simulation(stimulus, response))
self.assertTrue(self.duration <= now())
def test():
self.reset.next = False
yield self.clk.negedge
self.reset.next = True
yield self.rx_tick.posedge
prev_now = curr_now = now()
# run 3 tx cycles = 3 * rx_div
for i in range(3 * self.RX_DIV):
yield self.rx_tick.posedge
curr_now = now()
delta_now = curr_now - prev_now
delta = abs(delta_now - delta_tick)
self.assertTrue(delta <= 2,
'delta = %s, should max 2 (1 clock cycle)' % delta)
prev_now = curr_now
self.stop_simulation()
def testRedundantNegedges(self):
""" Redundant negedge waveform test """
s = self.sig
stimulus = self.stimulus()
expected = getExpectedTimes(self.waveform, isNegedge)
response = self.response(clause=(s.negedge,) * 9, expected=expected)
self.runSim(Simulation(stimulus, response))
assert self.duration <= now()
def testRedundantEvents(self):
""" Redundant event waveform test """
s = self.sig
stimulus = self.stimulus()
expected = getExpectedTimes(self.waveform, isEvent)
response = self.response(clause=(s,) * 6, expected=expected)
self.runSim(Simulation(stimulus, response))
assert self.duration <= now()
def testPosedge(self):
""" Posedge waveform test """
s = self.sig
stimulus = self.stimulus()
expected = getExpectedTimes(self.waveform, isPosedge)
response = self.response(clause=s.posedge, expected=expected)
self.runSim(Simulation(stimulus, response))
assert self.duration <= now()
def master():
i = 0
while 1:
yield clk.posedge
msig.next = uprange[i+1]
assert msig.val == uprange[i]
shared.t = now()
i += 1
def stimulus():
a = Signal(0)
def gen():
yield join(delay(10), delay(20))
yield gen(), delay(5)
self.assertEqual(now(), 5)
yield a
self.fail("Incorrect run") # should not get here
def master():
i = 0
while 1:
yield clk.posedge
msig.next = uprange[i+1]
self.assertEqual(msig.val, uprange[i])
shared.t = now()
i += 1
def testRedundantPosedges(self):
""" Redundant posedge waveform test """
s = self.sig
stimulus = self.stimulus()
expected = getExpectedTimes(self.waveform, isPosedge)
response = self.response(clause=(s.posedge,) * 3, expected=expected)
self.runSim(Simulation(stimulus, response))
self.assert_(self.duration <= now())
def stimulus():
header = "%-6s|%-6s|%-6s|%-6s|%-6s" % ('time', 'I0', 'I1', 'S', 'O')
print header + '\n' + '-' * len(header)
while True:
S.next = intbv(random.randint(0, 1))[1:]
I0.next, I1.next = [intbv(random.randint(0, 255))[32:] for i in range(2)]
print "%-6s|%-6s|%-6s|%-6s|%-6s" % (now(), I0, I1, S, O)
yield delay(5)