def checkname(self, name):
t_in = pyrtl.WireVector(name=name, bitwidth=3)
t_out = pyrtl.WireVector(name='t_out', bitwidth=3)
t_out <<= t_in + 1
with io.StringIO() as testbuffer:
pyrtl.output_to_verilog(testbuffer)
self.assertTrue(True)
def test_romblock_does_not_throw_error(self):
a = pyrtl.Input(bitwidth=3, name='a')
b = pyrtl.Input(bitwidth=3, name='b')
o = pyrtl.Output(bitwidth=3, name='o')
sum, co = generate_full_adder(a, b)
rdat = {0: 1, 1: 2, 2: 5, 5: 0}
mixtable = pyrtl.RomBlock(addrwidth=3, bitwidth=3, romdata=rdat)
o <<= mixtable[sum]
with io.StringIO() as testbuffer:
pyrtl.output_to_verilog(testbuffer)
def test_romblock_does_not_throw_error(self):
from pyrtl.corecircuits import _basic_add
a = pyrtl.Input(bitwidth=3, name='a')
b = pyrtl.Input(bitwidth=3, name='b')
o = pyrtl.Output(bitwidth=3, name='o')
res = _basic_add(a,b)
rdat = {0: 1, 1: 2, 2: 5, 5: 0}
mixtable = pyrtl.RomBlock(addrwidth=3, bitwidth=3, romdata=rdat)
o <<= mixtable[res[:-1]]
with io.StringIO() as testbuffer:
pyrtl.output_to_verilog(testbuffer)
def test_romblock_does_not_throw_error(self):
from pyrtl.corecircuits import _basic_add
a = pyrtl.Input(bitwidth=3, name='a')
b = pyrtl.Input(bitwidth=3, name='b')
o = pyrtl.Output(bitwidth=3, name='o')
res = _basic_add(a,b)
rdat = {0: 1, 1: 2, 2: 5, 5: 0}
mixtable = pyrtl.RomBlock(addrwidth=3, bitwidth=3, pad_with_zeros=True, romdata=rdat)
o <<= mixtable[res[:-1]]
with io.StringIO() as testbuffer:
pyrtl.output_to_verilog(testbuffer)
def test_textual_consistency(self):
from pyrtl.wire import _reset_wire_indexers
from pyrtl.memory import _reset_memory_indexer
# To compare textual consistency, need to make
# sure we're starting at the same index for all
# automatically created names.
_reset_wire_indexers()
_reset_memory_indexer()
# The following is a non-sensical program created to test
# that the Verilog that is created is deterministic
# in the order in which it presents the wire, register,
# and memory declarations and the combinational and
# sequential logic. Hence it creates many memories, and
# makes sure at least two lines of code are created in
# the always @ blocks associated with them (so we have
# many different wire names to deal with and test against).
a = pyrtl.Input(4, 'a')
r = pyrtl.Register(4)
s = pyrtl.Register(4)
# This will have mem id 0, so prints first despite actual name
mt = pyrtl.MemBlock(4, 2, name='z')
m = [pyrtl.MemBlock(4, 2, max_write_ports=2) for _ in range(12)]
for mem in m:
mem[0] <<= a
mem[1] <<= (r + 1).truncate(4)
b = a + r
r.next <<= b + 1 - s
s.next <<= a - 1
mt[0] <<= 9
o = pyrtl.Output(6, 'o')
o <<= b + m[0][0] + m[1][0]
buffer = io.StringIO()
pyrtl.output_to_verilog(buffer)
self.assertEqual(buffer.getvalue(), verilog_output)
counter_output <<= counter
# The counter gets 0 in the next cycle if the "zero" signal goes high, otherwise just
# counter + 1. Note that both "0" and "1" are bit extended to the proper length and
# here we are making use of that native add operation. Let's dump this bad boy out
# to a Verilog file and see what is looks like (here we are using StringIO just to
# print it to a string for demo purposes; most likely you will want to pass a normal
# open file).
print("--- PyRTL Representation ---")
print(pyrtl.working_block())
print()
print("--- Verilog for the Counter ---")
with io.StringIO() as vfile:
pyrtl.output_to_verilog(vfile)
print(vfile.getvalue())
print("--- Simulation Results ---")
sim_trace = pyrtl.SimulationTrace([counter_output, zero])
sim = pyrtl.Simulation(tracer=sim_trace)
for cycle in range(15):
sim.step({'zero': random.choice([0, 0, 0, 1])})
sim_trace.render_trace()
# We already did the "hard" work of generating a test input for this simulation, so
# we might want to reuse that work when we take this design through a Verilog toolchain.
# The class OutputVerilogTestbench grabs the inputs used in the simulation trace
# and sets them up in a standard verilog testbench.
print("--- Verilog for the TestBench ---")
counter_output <<= counter
# The counter gets 0 in the next cycle if the "zero" signal goes high, otherwise just
# counter + 1. Note that both "0" and "1" are bit extended to the proper length and
# here we are making use of that native add operation. Let's dump this bad boy out
# to a verilog file and see what is looks like (here we are using StringIO just to
# print it to a string for demo purposes, most likely you will want to pass a normal
# open file).
print("--- PyRTL Representation ---")
print(pyrtl.working_block())
print()
print("--- Verilog for the Counter ---")
with io.StringIO() as vfile:
pyrtl.output_to_verilog(vfile)
print(vfile.getvalue())
print("--- Simulation Results ---")
sim_trace = pyrtl.SimulationTrace([counter_output, zero])
sim = pyrtl.Simulation(tracer=sim_trace)
for cycle in range(15):
sim.step({zero: random.choice([0, 0, 0, 1])})
sim_trace.render_trace()
# We already did the "hard" work of generating a test input for this simulation so
# we might want to reuse that work when we take this design through a verilog toolchain.
# The function output_verilog_testbench grabs the inputs used in the simulation trace
# and sets them up in a standar verilog testbench.
print("--- Verilog for the TestBench ---")
