def run_xula():
brd = get_board('xula')
brd.add_port(**led_port_pin_map['xula'])
flow = build.flow.ISE(brd=brd, top=blinky)
flow.run()
info = flow.get_utilization()
pprint(info)
# get a board to implement the design on
brd = get_board('xula2')
brd.add_port(**led_port_pin_map['xula2'])
flow = build.flow.ISE(brd=brd, top=blinky)
flow.run()
info = flow.get_utilization()
pprint(info)
def run_nano():
brd = get_board('de0nano')
flow = build.flow.Quartus(brd=brd, top=blinky)
flow.run()
info = flow.get_utilization()
pprint(info)
flow.program()
def run_waxwing45carrier():
brd = get_board('waxwing45carrier')
brd.add_port_name(**led_port_pin_map['waxwing45carrier'])
flow = build.flow.ISE(brd=brd, top=blinky)
flow.run()
info = flow.get_utilization()
pprint(info)
def run_zybo():
# get a board to implement the design on
brd = get_board('zybo')
flow = build.flow.Vivado(brd=brd, top=blinky)
flow.run()
info = flow.get_utilization()
pprint(info)
def build():
global brd, flow
brd = get_board('de1soc')
# print("get_Board value{}".format(brd))
# print("get_flow value{}".format(flow))
flow = brd.get_flow(top=de1_soc_lt24lcd)
flow.run()
def run_zybo():
# get a board to implement the design on
brd = get_board('zybo')
flow = build.flow.Vivado(brd=brd, top=blinky)
flow.run()
info = flow.get_utilization()
pprint(info)
def build(args):
brd = get_board('ppro')
brd.add_port_name('uart_tx', 'tx')
brd.add_port_name('uart_rx', 'rx')
brd.add_port_name('led', 'winga', slc=slice(0,8))
flow = brd.get_flow(top=uart_blinky)
flow.run()
def build(args):
'''
3 GPIO for CTL OUTPUT 1 GPIO for CTL INPUT
CH14 B15 CH31 A2 CH22 H1 CH13 B16
BCM14 BCM2 BCM5 BCM15
GPIO FOR XULA2-LX9
8 GPIO FOR OUTPUT
CH6 K16 CH2 R16 CH4 M16 CH5 K15 CH12 C15 CH1 R15 CH3 M15 CH7 J16
BCM12 BCM19 BCM13 BCM6 BCM18 BCM20 BCM16 BCM7
8 GPIO FOR INPUT
CH23 H2 CH25 F2 CH27 E2 CH29 B1 CH24 F1 CH26 E1 CH28 C1 CH30 B2
BCM11 BCM10 BCM27 BCM4 BCM9 BCM22 BCM17 BCM3
'''
brd = get_board(args.brd)
#brd.device = 'XC6SLX9'
#brd.add_port_name('fr_rpi2B', 'pm1', slice(0, 8))
#brd.add_port_name('to_rpi2B', 'pm3', slice(0, 8))
brd.add_port('a_astb', 'R16')
brd.add_port('a_dstb', 'T15')
#brd.add_port('a_write', 'H1')
brd.add_port('a_wait', 'T14')
print(("%s %s") % (brd, brd.device))
flow = brd.get_flow(para_rpi2B)
flow.run()
def run_nano():
brd = get_board('de0nano')
flow = build.flow.Quartus(brd=brd, top=blinky)
flow.run()
info = flow.get_utilization()
pprint(info)
flow.program()
def run_pone():
brd = get_board('pone')
brd.add_port_name('toggle', 'wingC', 7, drive=6)
flow = build.flow.ISE(brd=brd, top=m_blink)
flow.run()
info = flow.get_utilization()
pprint(info)
def run_catboard():
# Get the CAT Board object.
brd = get_board('catboard')
# Add the ports and pin assignments for PMOD socket PM3.
brd.add_port('d0_o', 'A11')
brd.add_port('d1_o', 'B10')
brd.add_port('d2_o', 'B12')
brd.add_port('d3_o', 'B11')
brd.add_port('d4_o', 'B14')
brd.add_port('d5_o', 'B13')
brd.add_port('d6_o', 'B15')
brd.add_port('d7_o', 'A15')
# Add the clock port to the 100 MHz on-board oscillator.
brd.add_clock('master_clk_i', 1e8, 'C8')
# Route clocks to/from the SDRAM.
brd.add_port('sdram_clk_o', 'G16')
brd.add_clock('sdram_clk_i', 1e8, 'H16')
# Add the ports to the pushbuttons.
brd.add_port('pb_i', 'A16', PULLUP='PULLUP')
# Add the connections to the SDRAM.
brd.add_port('sdintf.cke', 'G15')
brd.add_port('sdintf.cs', 'H13')
brd.add_port('sdintf.cas', 'K15')
brd.add_port('sdintf.ras', 'K16')
brd.add_port('sdintf.we', 'J14')
brd.add_port('sdintf.bs', ('H14','G13'))
brd.add_port('sdintf.addr', ('F13','E14','E13','D14','B16','C16','D15','D16','E16','F15','F14','F16','G14'))
brd.add_port('sdintf.dqml', 'J13')
brd.add_port('sdintf.dqmh', 'J15')
brd.add_port('sdintf.dq', ('R14','P14','M13','M14','L13','L14','K13','K14','J16','L16','M16','M15','N16','P16','P15','R15'))
# Run the MyHDL+yosys+arachne-pnr design tools on the top-level module.
flow = brd.get_flow(top=sdram_test)
flow.run()
def build(args):
brd = get_board('catboard')
brd.add_port_name('uart_rx', 'bcm14_txd')
brd.add_port_name('uart_tx', 'bcm15_rxd')
brd.add_reset('reset', active=0, async=True, pins=('N11',))
flow = brd.get_flow(top=catboard_blinky_host)
flow.run()
def compile_mojo():
brd = get_board('mojo')
brd.add_port('button', pins=51, pullup=True) # you can plug directly a button there between pin51 and gnd.
flow = brd.get_flow(top=snow)
flow.run()
info = flow.get_utilization()
pprint(info)
def run_nano():
brd = get_board('de0nano_soc')
brd.add_port('toggle', pins=("W15",))
flow = build.flo.Quartus(brd=brd, top=m_blink)
flow.run(use='vhdl')
info = flow.get_utilization()
pprint(info)
def build(args):
brd = get_board('ppro')
brd.add_port_name('uart_tx', 'tx')
brd.add_port_name('uart_rx', 'rx')
brd.add_port_name('led', 'winga', slc=slice(0, 8))
flow = brd.get_flow(top=uart_blinky)
flow.run()
def print_board_info(args):
boards = get_all_board_names()
for bn in boards:
brd = get_board(bn)
has_led = False
led = brd.get_port('led')
if led is None:
led = brd.get_port('leds')
if led is not None:
has_led = True
numled = 0 if led is None else len(led.pins)
ledpins = ' ' if led is None else led.pins
ledname = ' ' if led is None else led.name
# print some information
print("{:12}: has led {:5}: {:5}, # led {}, led pins {} ".format(
bn,
str(has_led),
str(ledname),
numled,
str(ledpins),
))
return
def build(args):
brd = get_board('xula2_stickit_mb')
brd.add_port_name('led', 'pm2', slice(0, 8))
brd.add_reset('reset', active=0, async=True, pins=('H2',))
flow = brd.get_flow(top=xula2_blinky_host)
flow.run()
info = flow.get_utilization()
pprint(info)
def build(args):
brd = get_board('xula2_stickit_mb')
brd.add_port_name('led', 'pm2', slice(0, 8))
brd.add_reset('reset', active=0, async=True, pins=('H2', ))
flow = brd.get_flow(top=xula2_blinky_host)
flow.run()
info = flow.get_utilization()
pprint(info)
def run_nano():
brd = get_board('de0cv')
brd.add_port_name('led','ledr')
flow = build.flow.Quartus(brd=brd, top=blinky)
flow.run()
info = flow.get_utilization()
pprint(info)
flow.program()
def run_nano():
brd = get_board('de0nano')
brd.add_port('toggle', pins=("A15",))
flow = build.flow.Quartus(brd=brd, top=m_blink)
flow.run()
info = flow.get_utilization()
pprint(info)
flow.program()
def impl():
from rhea.build.boards import get_board
brd = get_board('sds7102')
flow = brd.get_flow(top = top)
flow.run()
info = flow.get_utilization()
pprint(info)
def run_ppro():
brd = get_board('ppro')
#brd.add_port_name('toggle', 'wingC', 7, drive=6)
brd.add_port_name(**led_port_pin_map['ppro'])
flow = build.flow.ISE(brd=brd, top=blinky)
flow.run()
info = flow.get_utilization()
pprint(info)
def run_xula():
brd = get_board('xula')
brd.add_port('toggle', pins=(36,))
brd.add_reset('reset', active=0, async=True, pins=(37,))
flow = build.flow.ISE(brd=brd, top=m_blink)
flow.run()
info = flow.get_utilization()
pprint(info)
# get a board to implement the design on
brd = get_board('xula2')
brd.add_port('toggle', pins=('R7',))
brd.add_reset('reset', active=0, async=True, pins=('R15',))
flow = build.flow.ISE(brd=brd, top=m_blink)
flow.run()
info = flow.get_utilization()
pprint(info)
def run_catboard():
brd = get_board('catboard')
#BCM15
brd.add_port('rx', 'T14')
#BCM14
brd.add_port('tx', 'T15')
flow = brd.get_flow(top=tx_rx)
flow.run()
def compile_mojo():
brd = get_board('mojo')
brd.add_port(
'button', pins=51, pullup=True
) # you can plug directly a button there between pin51 and gnd.
flow = brd.get_flow(top=snow)
flow.run()
info = flow.get_utilization()
pprint(info)
def run_xula2():
brd = get_board('xula2')
brd.device = 'XC6SLX9'
#BCM25
brd.add_port('mosi', 'F2')
#BCM24
brd.add_port('miso', 'F1')
flow = brd.get_flow(top=spi)
flow.run()
def run_zybo():
# get a board to implement the design on
brd = get_board('zybo')
brd.add_port('toggle', pins=('R7',))
brd.add_reset('reset', active=0, async=True, pins=('R15',))
flow = build.flow.Vivado(brd=brd, top=m_blink)
flow.run()
info = flow.get_utilization()
pprint(info)
def build(args):
brd = get_board(args.brd)
# the design port names don't match the board pin names,
# add the ports here (all the IO are a generic "chan")
brd.add_port(**led_port_pin_map[args.brd])
brd.add_port(name='button', pins=(33, ))
flow = brd.get_flow(xula_blink)
flow.run()
info = flow.get_utilization()
pprint(info)
def build(args):
brd = get_board(args.brd)
# the design port names don't match the board pin names,
# add the ports here (all the IO are a generic "chan")
brd.add_port(**led_port_pin_map[args.brd])
brd.add_port(name='button', pins=(33,))
flow = brd.get_flow(xula_blink)
flow.run()
info = flow.get_utilization()
pprint(info)
def program():
global flow
if flow is not None:
pass
else:
brd = get_board('de0nano_soc')
flow = build.flow.Quartus(brd=brd, top=de0nano_soc_device_prims)
print("program board")
flow.program()
print("programming finished")
def test_boards():
for bn in get_all_board_names():
brd = get_board(bn)
# map led port for boards without explicit led pins
if bn in led_port_pin_map:
brd.add_port_name(**led_port_pin_map[bn])
flow = build.flow.Yosys(brd=brd, top=blinky)
flow.path = os.path.join('output', flow.path)
flow.run()
def test_boards():
for bn in get_all_board_names():
brd = get_board(bn)
# map led port for boards without explicit led pins
if bn in led_port_pin_map:
brd.add_port_name(**led_port_pin_map[bn])
flow = build.flow.Yosys(brd=brd, top=blinky)
flow.path = os.path.join('output', flow.path)
flow.run()
def run_catboard():
# Get the CAT Board object.
brd = get_board('catboard')
#BCM23
brd.add_port('ss0', 'P9')
#BCM15
brd.add_port('clkInOut', 'T14')
#BCM27
brd.add_port('ld_o', 'R10')
flow = brd.get_flow(top=top_sending)
flow.run()
def program():
global flow
if flow is not None:
pass
else:
brd = get_board('cmoda7_' + variant)
flow = brd.get_flow(top=cmoda7_device_prim)
print("program board")
flow.program()
print("programming finished")
def program():
global flow
if flow is not None:
pass
else:
brd = get_board('zybo')
flow = brd.get_flow(top=zybo_device_prim)
print("program board")
flow.program()
print("programming finished")
def program():
global flow
if flow is not None:
pass
else:
brd = get_board('cmoda7_' + variant)
flow = brd.get_flow(top=cmoda7_device_prim)
print("program board")
flow.program()
print("programming finished")
def test_iceriver():
"""
This test is identical to ex_icestick but it is
automatically run by the py.test test runner.
This test verifies the flow completes without
error.
"""
brd = get_board('icestick')
flow = brd.get_flow(top=blinky)
flow.path = os.path.join('output', flow.path)
flow.run()
def run_xula2board():
# Get the CAT Board object.
brd = get_board('xula2')
brd.device = 'XC6SLX9'
#CHAN11
brd.add_port('ss0', 'C16')
#CHAN13
brd.add_port('clkInOut', 'B16')
#CHAN27
brd.add_port('ld_o', 'E2')
flow = brd.get_flow(top=top_sending)
flow.run()
def build_board(args):
"""
"""
boards = get_all_board_names() if args.board == 'all' else [args.board]
for bn in boards:
brd = get_board(bn)
if brd in led_port_pin_map:
brd.add_port_name(**led_port_pin_map[brd])
ledport = brd.get_port('led')
return
def build(args):
'''
GPIO FOR XULA2-LX9
16 GPIO FOR INPUT OR OUTPUT
CH0 R7 CH1 R15 CH2 R16 CH3 M15 CH4 M16 CH5 K15 CH6 K16 CH7 J16
CH8 J14 CH9 F15 CH10 F16 CH11 C16 CH12 C15 CH13 B16 CH14 B15 CH22 H1
CH23 H2 CH24 F1 CH25 F2 CH26 E1
CH27 E2 CH28 C1 CH29 B1 B30 B2 CH31 A2
'''
brd = get_board(args.brd)
brd.device = 'XC6SLX9'
print(("%s %s") % (brd, brd.device))
def program():
global flow
if flow is not None:
pass
else:
brd = get_board('de0nano_soc')
flow = build.flow.Quartus(brd=brd,
top=de0nano_soc_device_prims)
print("program board")
flow.program()
print("programming finished")
def compile():
brd = get_board('xula')
# Set the ports for the design (top-level) and the
# signal type for the ports. If the port name matches
# one of the FPGA default port names they do not need
# to be remapped.
brd.add_port('button', pins=(33, ))
brd.add_port('led', pins=(32, ))
flow = build.flow.ISE(brd=brd, top=m_button_led)
flow.run()
info = flow.get_utilization()
pprint(info)
def build_board(args):
"""
"""
boards = get_all_board_names() if args.board == 'all' else [args.board]
for bn in boards:
brd = get_board(bn)
if brd in led_port_pin_map:
brd.add_port(**led_port_pin_map[brd])
# check the board definition has led port, if not add it from
# the board_table
ledport = brd.get_port('led')
return
def build():
# get the development board the design is targetting
brd = get_board('xula2')
# Set the ports for the design (top-level) and the
# signal type for the ports. If the port name matches
# one of the FPGA default port names they do not need
# to be remapped.
brd.add_port(name='led', pins=('T7', ))
# assign the top-level HDL module (python function)
# as the top-level
flow = brd.get_flow(strobe)
flow.run()
info = flow.get_utilization()
pprint(info)
def build():
# get the development board the design is targetting
brd = get_board('xula2')
# chinese driver; PM3 GR2-D2 = F2
# IC HAUS; M2 is pin6 using DEFAULT PMOD Numbers
brd.add_port(name='laserpin', pins=('r16', )) #i.e.
brd.add_reset('reset', active=1, async=True, pins=('E1', )) #i.e. BCM22
#NOTE: TO measure the voltage level,
# look at the top of the board, the connections toward you
# stickit socket are bottem, photodiode pin is upper richt most
# connect ground via PMOD
# assign the top-level HDL module (python function)
# as the top-level
flow = brd.get_flow(laserdriver)
flow.run()
info = flow.get_utilization()
print(info)
def build():
# get the development board the design is targetting
brd = get_board('xula2')
# Set the ports for the design (top-level) and the
# signal type for the ports. If the port name matches
# one of the FPGA default port names they do not need
# to be remapped.
brd.add_port(name='polypin', pins=('t7', )) # i.e. PM1 GR1-D1
brd.add_reset('resetpoly', active=1, async=True,
pins=('E1', )) # i.e. BCM 22
# assign the top-level HDL module (python function)
# as the top-level
flow = brd.get_flow(polydriver)
flow.run()
info = flow.get_utilization()
print(info)
def run_catboard():
# Get the CAT Board object.
brd = get_board('catboard')
# Add the ports and pin assignments for PMOD socket PM3.
brd.add_port('d0_o', 'A11')
brd.add_port('d1_o', 'B10')
brd.add_port('d2_o', 'B12')
brd.add_port('d3_o', 'B11')
brd.add_port('d4_o', 'B14')
brd.add_port('d5_o', 'B13')
brd.add_port('d6_o', 'B15')
brd.add_port('d7_o', 'A15')
# Add the clock port to the 100 MHz on-board oscillator.
brd.add_clock('clk_i', 1e8, 'C8')
# Add the ports to the pushbuttons.
brd.add_port('sw1_i', 'A16', PULLUP='PULLUP')
brd.add_port('sw2_i', 'B9', PULLUP='PULLUP')
# Add the four-bit port to the DIP switch.
brd.add_port('sw3_i', ('C6', 'C5', 'C4', 'C3'), PULLUP='PULLUP')
# Run the MyHDL+yosys+arachne-pnr design tools on the top-level module.
flow = brd.get_flow(top=buttons_display)
flow.run()
def build():
# get the development board the design is targetting
brd = get_board('xula2')
# Set the ports for the design (top-level) and the
# signal type for the ports. If the port name matches
# one of the FPGA default port names they do not need
# to be remapped.
# XULA --> STEPPER
brd.add_port(name='step_pino', pins=('e2', )) # D4, PM3
brd.add_port(name='dir_pino', pins=('c1', )) # D5, PM3
# RASPBERRY --> XULA
brd.add_port(name='dir_pini', pins=('k16', )) # BCM 12
brd.add_port(name='en_pini', pins=('m16', )) # BCM 13
brd.add_reset('reset', active=1, async=True, pins=('E1', )) # BCM 22
# assign the top-level HDL module (python function)
# as the top-level
flow = brd.get_flow(stepperdriver)
flow.run()
info = flow.get_utilization()
print(info)
def build(args):
brd = get_board('atlys')
flow = brd.get_flow(top=atlys_blinky_host)
flow.run()
def build(args):
brd = get_board('de0nano')
flow = brd.get_flow(de0nano_blink)
flow.run()
info = flow.get_utilization()
pprint(info)
def run_catboard():
brd = get_board('catboard')
flow = brd.get_flow(top=blinky)
flow.run()
def build():
brd = get_board('zybo')
flow = brd.get_flow(zybo_blink)
flow.run()
def build_bitfile():
global flow
brd = get_board('de0nano_soc')
flow = build.flow.Quartus(brd=brd, top=de0nano_soc_device_prims)
flow.run(use='verilog')
