def simulate(self, # pylint: disable=too-many-arguments, too-many-locals output_path, library_name, entity_name, architecture_name, config, elaborate_only=False): """ Elaborates and Simulates with entity as top level using generics """ launch_gui = self._gui is not False and not elaborate_only cmd = join(self._prefix, 'vcs') copy_file(self._vcssetup, output_path) vcsargs = [] vcsargs += ['%s' % join('%s.%s' % (library_name, entity_name))] if not launch_gui: vcsargs += ['-ucli'] vcsargs += ['-licqueue'] vcsargs += ['-debug_all'] if not self._log_level == "debug": vcsargs += ['-q'] vcsargs += ['-nc'] else: vcsargs += ['-V'] vcsargs += ['-notice'] vcsargs += ['-l %s/vcs.log' % (output_path)] generics = self._generic_args(entity_name, config.generics) genericsfile = "%s/vcs.generics" % (output_path) write_file(genericsfile, "\n".join(generics)) vcsargs += ['-lca', '-gfile %s' % genericsfile] if config.options.get('vcs_sim_flags'): vcsargs += config.options.get('vcs_sim_flags') vcsargsfile = '%s/vcs.args' % output_path write_file(vcsargsfile, "\n".join(vcsargs)) if not run_command([cmd, '-full64', '-file', vcsargsfile], cwd=output_path): return False cmd = join(output_path, 'simv') simvargs = [] simvargs += ['-l %s/simv.log' % (output_path)] dofile = '%s/simv.do' % output_path docmds = [] if launch_gui: simvargs += ['-gui'] docmds += [''] else: simvargs += ['-ucli'] simvargs += ['-do "%s"' % dofile] docmds += ['# senv'] docmds += ['# config'] docmds += ['# package require tcldoc'] docmds += ['run'] docmds += ['catch {show -value "/vunit_pkg/__runner__/exit_without_errors"}'] docmds += ['catch {show -value "/run_base_pkg/runner/exit_without_errors"}'] docmds += ['catch {set foo [get /run_base_pkg/runner/exit_without_errors]; if {$foo == TRUE} {tcl_exit 0} else {tcl_exit 42}}'] docmds += ['catch {set foo [get /vunit_pkg/__runner__/exit_without_errors]; if {$foo == 1} {tcl_exit 0} else {tcl_exit 42}}'] write_file(dofile, "\n".join(docmds)) simvargsfile = '%s/simv.args' % output_path write_file(simvargsfile, "\n".join(simvargs)) if not elaborate_only: if not run_command([cmd, ' '.join(simvargs)], cwd=output_path): return False return True
def simulate(self, # pylint: disable=too-many-locals output_path, test_suite_name, config, elaborate_only=False): """ Elaborates and Simulates with entity as top level using generics """ script_path = join(output_path, self.name) launch_gui = self._gui is not False and not elaborate_only if elaborate_only: steps = ['elaborate'] else: steps = ['elaborate', 'simulate'] for step in steps: cmd = join(self._prefix, 'irun') args = [] if step == 'elaborate': args += ['-elaborate'] args += ['-nocopyright'] args += ['-licqueue'] # args += ['-dumpstack'] # args += ['-gdbsh'] # args += ['-rebuild'] # args += ['-gdb'] # args += ['-gdbelab'] args += ['-errormax 10'] args += ['-nowarn WRMNZD'] args += ['-nowarn DLCPTH'] # "cds.lib Invalid path" args += ['-nowarn DLCVAR'] # "cds.lib Invalid environment variable ''." args += ['-ncerror EVBBOL'] # promote to error: "bad boolean literal in generic association" args += ['-ncerror EVBSTR'] # promote to error: "bad string literal in generic association" args += ['-ncerror EVBNAT'] # promote to error: "bad natural literal in generic association" args += ['-work work'] args += ['-nclibdirname "%s"' % (join(self._output_path, "libraries"))] # @TODO: ugly args += config.sim_options.get('incisive.irun_sim_flags', []) args += ['-cdslib "%s"' % self._cdslib] args += self._hdlvar_args() args += ['-log "%s"' % join(script_path, "irun_%s.log" % step)] if not self._log_level == "debug": args += ['-quiet'] else: args += ['-messages'] # args += ['-libverbose'] args += self._generic_args(config.entity_name, config.generics) for library in self._libraries: args += ['-reflib "%s"' % library.directory] if launch_gui: args += ['-access +rwc'] # args += ['-linedebug'] args += ['-gui'] else: args += ['-access +r'] args += ['-input "@run"'] if config.architecture_name is None: # we have a SystemVerilog toplevel: args += ['-top %s' % join('%s.%s:sv' % (config.library_name, config.entity_name))] else: # we have a VHDL toplevel: args += ['-top %s' % join('%s.%s:%s' % (config.library_name, config.entity_name, config.architecture_name))] argsfile = "%s/irun_%s.args" % (script_path, step) write_file(argsfile, "\n".join(args)) if not run_command([cmd, '-f', relpath(argsfile, script_path)], cwd=script_path, env=self.get_env()): return False return True
def simulate( self, # pylint: disable=too-many-locals output_path, test_suite_name, config, elaborate_only=False): """ Elaborates and Simulates with entity as top level using generics """ launch_gui = self._gui is not False and not elaborate_only if elaborate_only: steps = ['elaborate'] else: steps = ['elaborate', 'simulate'] for step in steps: cmd = join(self._prefix, 'irun') args = [] if step == 'elaborate': args += ['-elaborate'] args += ['-nocopyright'] args += ['-licqueue'] # args += ['-dumpstack'] # args += ['-gdbsh'] # args += ['-rebuild'] # args += ['-gdb'] # args += ['-gdbelab'] args += ['-errormax 10'] args += ['-nowarn WRMNZD'] args += ['-nowarn DLCPTH'] # "cds.lib Invalid path" args += ['-nowarn DLCVAR' ] # "cds.lib Invalid environment variable ''." args += [ '-ncerror EVBBOL' ] # promote to error: "bad boolean literal in generic association" args += [ '-ncerror EVBSTR' ] # promote to error: "bad string literal in generic association" args += [ '-ncerror EVBNAT' ] # promote to error: "bad natural literal in generic association" args += ['-work work'] args += [ '-nclibdirname "%s"' % (join(self._output_path, "libraries")) ] # @TODO: ugly args += config.sim_options.get('incisive.irun_sim_flags', []) args += ['-cdslib "%s"' % self._cdslib] args += self._hdlvar_args() args += ['-log "%s/irun_%s.log"' % (output_path, step)] if not self._log_level == "debug": args += ['-quiet'] else: args += ['-messages'] # args += ['-libverbose'] args += self._generic_args(config.entity_name, config.generics) for library in self._libraries: args += ['-reflib "%s"' % library.directory] if launch_gui: args += ['-access +rwc'] # args += ['-linedebug'] args += ['-gui'] else: args += ['-access +r'] args += ['-input "@run"'] # Try hierarchical path formats for both VHDL and Verilog, but don't throw an error if not found. # args += ['-input "@catch {puts #vunit_pkg::__runner__.exit_without_errors}"'] # args += ['-input "@catch {puts #run_base_pkg.runner.exit_without_errors}"'] # NOTE: do not exit with 1 or 2 in case of error, that seems to mean something special to Incisive: args += [ '-input "@catch ' '{if {#vunit_pkg::__runner__.exit_without_errors == 1} {exit 0} else {exit 42}}"' ] args += [ '-input "@catch ' '{if {#run_base_pkg.runner.exit_without_errors == \\"TRUE\\"} {exit 0} else {exit 42}}"' ] if config.architecture_name is None: # we have a SystemVerilog toplevel: args += [ '-top %s' % join('%s.%s:sv' % (config.library_name, config.entity_name)) ] else: # we have a VHDL toplevel: args += [ '-top %s' % join('%s.%s:%s' % (config.library_name, config.entity_name, config.architecture_name)) ] argsfile = "%s/irun_%s.args" % (output_path, step) write_file(argsfile, "\n".join(args)) if not run_command( [cmd, '-f', relpath(argsfile, output_path)], cwd=output_path, env=self.get_env()): return False return True
def simulate(self, # pylint: disable=too-many-arguments, too-many-locals output_path, library_name, entity_name, architecture_name, config, elaborate_only=False): """ Elaborates and Simulates with entity as top level using generics """ launch_gui = self._gui is not False and not elaborate_only if elaborate_only: steps = ['elaborate'] else: steps = ['elaborate', 'simulate'] for step in steps: if step == 'elaborate': cmd = join(self._prefix, 'vcs') copy_file(self._vcssetup, output_path) args = [] args += ['-licqueue'] args += ['-debug_all'] # args += ['+vhdllib+work+vunit_lib+lib+'] # FIXME if not self._log_level == "debug": args += ['-q'] args += ['-nc'] else: args += ['-V'] args += ['-notice'] args += ['+libverbose'] #2 if launch_gui: #2 args += ['-debug_access+all'] #2 #args += ['-linedebug'] #2 args += ['-gui'] #2 else: #2 args += ['-debug_access+r'] #4 args += ['+libext++.v+.sv+.vams'] # means "no extension or .v, .sv, .vams" #4 args += ['+libext++'] # means "no extension" # args += ['-Mlib=%s/libraries' % self._output_path] # only for Verilog libraries #3 for library in self._libraries: #4 args += ['-y %s' % library.directory] # only for Verilog libraries # "-Mlib=<directory> # Specifies the directory where VCS looks for descriptor information # to see if a module needs to be recompiled. Also specifies a central # place for object files. You use this option for shared incremental # compilation." #3 args += ['-Mlib=%s' % library.directory] args += ['-l %s/vcs_%s.log' % (output_path, step)] # args += ['-top %s' % join('%s.%s' % (library_name, entity_name))] ## args += ['%s' % join('%s.%s' % (library_name, entity_name))] args += ['%s' % join('%s' % (entity_name))] argsfile = "%s/vcs_%s.args" % (output_path, step) write_file(argsfile, "\n".join(args)) if not run_command([cmd, '-full64', '-file', argsfile], cwd=output_path): return False if step == 'simulate': cmd = './simv' # generics for VHDL generics = self._generic_args(entity_name, config.generics) genericsfile = "%s/vcs_%s.generics" % (output_path, step) write_file(genericsfile, "\n".join(generics)) # parameters for Verilog (still take the value from "config.generics") parameters = self._parameter_args(entity_name, config.generics) parametersfile = "%s/vcs_%s.parameters" % (output_path, step) write_file(parametersfile, "\n".join(parameters)) args = [] # args += ['-lca', '-g %s' % genericsfile, '-parameters %s' % parametersfile] args += ['-lca', '-g %s' % genericsfile] if config.options.get('vcs_sim_flags'): args += config.options.get('vcs_sim_flags') args += ['-l %s/vcs_%s.log' % (output_path, step)] docmds = [] if not self._log_level == "debug": args += ['-q'] args += ['-nc'] if launch_gui: args += ['-gui'] docmds += [''] else: docmds += ['run; exit\n'] dofile = "%s/vcs_%s.do" % (output_path, step) write_file(dofile, "\n".join(docmds)) argsfile = "%s/vcs_%s.args" % (output_path, step) write_file(argsfile, "\n".join(args)) if not run_command([cmd, '-f', argsfile, '-ucli', '-do %s' % dofile], cwd=output_path): return False return True
def simulate(self, # pylint: disable=too-many-arguments, too-many-locals output_path, library_name, entity_name, architecture_name, config, elaborate_only=False): """ Elaborates and Simulates with entity as top level using generics """ launch_gui = self._gui is not False and not elaborate_only if elaborate_only: steps = ['elaborate'] else: steps = ['elaborate', 'simulate'] for step in steps: cmd = join(self._prefix, 'irun') args = [] if step == 'elaborate': args += ['-elaborate'] args += ['-nocopyright'] args += ['-licqueue'] # args += ['-dumpstack'] # args += ['-gdbsh'] # args += ['-rebuild'] # args += ['-gdb'] # args += ['-gdbelab'] args += ['-errormax 10'] args += ['-nowarn WRMNZD'] args += ['-nowarn DLCPTH'] # "cds.lib Invalid path" args += ['-nowarn DLCVAR'] # "cds.lib Invalid environment variable ''." args += ['-ncerror EVBBOL'] # promote to error: "bad boolean literal in generic association" args += ['-ncerror EVBSTR'] # promote to error: "bad string literal in generic association" args += ['-ncerror EVBNAT'] # promote to error: "bad natural literal in generic association" args += ['-work work'] args += ['-nclibdirname "%s"' % (join(self._output_path, "libraries"))] # @TODO: ugly args += config.options.get('incisive.irun_sim_flags', []) args += ['-cdslib "%s"' % self._cdslib] args += self._hdlvar_args() args += ['-log "%s/irun_%s.log"' % (output_path, step)] if not self._log_level == "debug": args += ['-quiet'] else: args += ['-messages'] # args += ['-libverbose'] args += self._generic_args(entity_name, config.generics) for library in self._libraries.values(): args += ['-reflib "%s"' % library.directory] if launch_gui: args += ['-access +rwc'] # args += ['-linedebug'] args += ['-gui'] else: args += ['-access +r'] args += ['-input "@run"'] # Try hierarchical path formats for both VHDL and Verilog, but don't throw an error if not found. # args += ['-input "@catch {puts #vunit_pkg::__runner__.exit_without_errors}"'] # args += ['-input "@catch {puts #run_base_pkg.runner.exit_without_errors}"'] # NOTE: do not exit with 1 or 2 in case of error, that seems to mean something special to Incisive: args += ['-input "@catch ' '{if {#vunit_pkg::__runner__.exit_without_errors == 1} {exit 0} else {exit 42}}"'] args += ['-input "@catch ' '{if {#run_base_pkg.runner.exit_without_errors == \\"TRUE\\"} {exit 0} else {exit 42}}"'] if architecture_name is None: # we have a SystemVerilog toplevel: args += ['-top %s' % join('%s.%s:sv' % (library_name, entity_name))] else: # we have a VHDL toplevel: args += ['-top %s' % join('%s.%s:%s' % (library_name, entity_name, architecture_name))] argsfile = "%s/irun_%s.args" % (output_path, step) write_file(argsfile, "\n".join(args)) if not run_command([cmd, '-f', relpath(argsfile, output_path)], cwd=output_path): return False return True