def main():
cli = VUnitCLI()
cli.parser.add_argument(
"--seed",
action="store",
help="Random seed for the tests",
type=int,
default=random.randint(-1 << 31, 1 << 31), # VHDL integer range
)
args = cli.parse_args()
print(f"Seed: {args.seed}")
cli = VUnit.from_args(args=args)
cli.add_osvvm()
cli.enable_location_preprocessing()
cli.add_com()
if cli.get_simulator_name() == "ghdl":
cli.add_preprocessor(GhdlPragmaHandler())
cli.add_library("fpga_cores").add_source_files(p.join(
ROOT, "src", "*.vhd"))
cli.add_library("str_format").add_source_files(
p.join(ROOT, "dependencies", "hdl_string_format", "src", "*.vhd"))
cli.add_library("tb")
cli.library("tb").add_source_files(p.join(ROOT, "testbench", "*.vhd"))
cli.add_library("fpga_cores_sim")
cli.library("fpga_cores_sim").add_source_files(p.join(
ROOT, "sim", "*.vhd"))
cli.add_library("exp_golomb").add_source_files(
p.join(ROOT, "src", "exponential_golomb", "*.vhd"))
addTests(cli, args.seed)
cli.set_compile_option("modelsim.vcom_flags", ["-explicit"])
# Not all options are supported by all GHDL backends
# cli.set_compile_option("ghdl.a_flags", ["-frelaxed-rules"])
# cli.set_compile_option("ghdl.a_flags", ["-frelaxed-rules", "-O0", "-g"])
cli.set_compile_option("ghdl.a_flags", ["-frelaxed-rules", "-O2", "-g"])
# Make components not bound (error 3473) an error
cli.set_sim_option("modelsim.vsim_flags",
["-error", "3473", '-voptargs="+acc=n"'])
# cli.set_sim_option("ghdl.sim_flags", ["-frelaxed-rules"])
# cli.set_sim_option("ghdl.elab_e", ["-frelaxed-rules"])
cli.set_sim_option("ghdl.elab_flags", ["-frelaxed-rules"])
cli.set_sim_option("disable_ieee_warnings", True)
cli.set_sim_option("modelsim.init_file.gui", p.join(ROOT, "wave.do"))
cli.main()
def main():
"Main entry point for DVB FPGA test runner"
_generateGnuRadioData()
_createLdpcTables()
cli = VUnitCLI()
cli.parser.add_argument(
"--individual-config-runs",
"-i",
action="store_true",
help="Create individual test runs for each configuration. By default, "
"all combinations of frame types, code rates and modulations are "
"tested in the same simulation",
)
args = cli.parse_args()
vunit = VUnit.from_args(args=args)
setupSources(vunit)
setupTests(vunit, args)
vunit.set_compile_option("modelsim.vcom_flags", ["-explicit"])
# Not all options are supported by all GHDL backends
vunit.set_sim_option("ghdl.elab_flags", ["-frelaxed-rules"])
vunit.set_compile_option("ghdl.a_flags", ["-frelaxed-rules", "-O2", "-g"])
# Make components not bound (error 3473) an error
vsim_flags = ["-error", "3473"]
if args.gui:
vsim_flags += ['-voptargs="+acc=n"']
vunit.set_sim_option("modelsim.vsim_flags", vsim_flags)
vunit.set_sim_option("disable_ieee_warnings", True)
vunit.set_sim_option("modelsim.init_file.gui", p.join(ROOT, "wave.do"))
vunit.main()
