def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
module.add_local_interface_template(AXIMasterExternal())
toplevel_file = "hardware/hdl/vhdl/AXI/AXI_Master.vhd"
module.files = []
module.dependencies = []
module.show_in_browser = True
module.dev_status = AsModule.DevStatus.STABLE
module.module_type = AsModule.ModuleTypes.HARDWARE
module.module_category = "IO Infrastructure"
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
internal_memory = module.get_interface("out")
internal_memory.to_external = False
internal_memory.instantiate_in_top = None
module.get_generic("C_M_AXI_DATA_WIDTH").set_value(None)
module.get_generic("C_M_AXI_ADDR_WIDTH").set_value(None)
module.brief_description = "AXI Master interface. Usually automatically inserted by Automatics. Contains Xilinx-specific HDL code!"
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
toplevel_file = "hardware/hdl/vhdl/as_iic.vhd"
module.files = []
module.dependencies = ["helpers", "as_regmgr"]
module.add_local_interface_template(IIC_Interface())
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module("{mdir}/{toplevel}".format(mdir=module_dir,
toplevel=toplevel_file))
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
module.add_local_interface_template(SWRegInterface())
toplevel_file = "hardware/hdl/vhdl/register_interface/as_regmgr.vhd"
module.files = [("hardware/hdl/vhdl/register_interface/"
"as_generic_regslice.vhd")]
module.dependencies = ["helpers"]
module.show_in_browser = False
module.dev_status = AsModule.DevStatus.STABLE
module.module_type = AsModule.ModuleTypes.HARDWARE
module.module_category = "Internal Submodules"
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
# Configuration method. This method is automatically executed
# by Automatics during the connection process, only if the module was
# automatically instantiated.
# This way we can access information only available at runtime.
def auto_inst_config(mod, inst_from):
# inst_from is the module that automatically instantiated this module
# mod is the instance of this module that was automatically instantiated
mod.set_generic_value("REG_ADDR_WIDTH", "c_slave_reg_addr_width")
mod.set_generic_value("REG_DATA_WIDTH", "C_S_AXI_DATA_WIDTH")
mod.set_generic_value("MODULE_ADDR_WIDTH", "c_module_addr_width")
base_addr_generic = vstatic.REGMGR_BASEADDR_VAL.format(inst_from.name)
mod.set_generic_value("MODULE_BASEADDR", base_addr_generic)
regmgr_count = "_" + mod.name[-1] if mod.name[-1].isdigit() else ""
target = vstatic.REGMGR_SW_DATA_OUT_TARGET.format(
inst_from.name, regmgr_count)
mod.set_port_fixed_value("sw_data_out", target)
if not regmgr_count:
regif = inst_from.register_ifs[0]
else:
regif = inst_from.register_ifs[int(regmgr_count.strip("_"))]
mod.set_generic_value("REG_COUNT", str(regif.get_reg_count()))
mod.get_interface("out",
if_type="slv_reg_interface").to_external = False
# !Important! Assign the configuration function to this module instance
module.auto_inst_config = auto_inst_config
# Return the module instance to Automatics
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
toplevel_file = "hardware/hdl/vhdl/as_iic.vhd"
module.files = []
module.dependencies = ["helpers", "as_regmgr"]
module.show_in_browser = True
module.dev_status = AsModule.DevStatus.BETA
module.module_type = AsModule.ModuleTypes.HARDWARE_SW_CTRL
module.module_category = "External IO"
module.add_local_interface_template(IIC_Interface())
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
module.add_local_interface_template(AXISlaveExternal())
toplevel_file = "hardware/hdl/vhdl/AXI/AXI_Slave.vhd"
module.files = []
module.dependencies = ["fifo_fwft", "helpers"]
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module("{mdir}/{toplevel}".format(mdir=module_dir,
toplevel=toplevel_file))
module.get_generic("C_S_AXI_DATA_WIDTH").set_value(None)
module.get_generic("C_S_AXI_ADDR_WIDTH").set_value(None)
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
toplevel_file = "hardware/hdl/vhdl/ram/ram.vhd"
module.files = []
module.dependencies = []
module.show_in_browser = False
module.dev_status = AsModule.DevStatus.STABLE
module.module_type = AsModule.ModuleTypes.HARDWARE
module.module_category = "Internal Submodules"
module.add_local_interface_template(SimpleRAMInterface())
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
module.add_local_interface_template(AXISlaveExternal())
toplevel_file = "hardware/hdl/vhdl/AXI/AXI_Slave.vhd"
module.files = []
module.dependencies = ["fifo_fwft", "helpers"]
module.show_in_browser = True
module.dev_status = AsModule.DevStatus.STABLE
module.module_type = AsModule.ModuleTypes.HARDWARE
module.module_category = "IO Infrastructure"
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
module.get_generic("C_S_AXI_DATA_WIDTH").set_value(None)
module.get_generic("C_S_AXI_ADDR_WIDTH").set_value(None)
module.brief_description = (
"AXI Slave interface. Usually automatically inserted by Automatics.")
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
module.add_local_interface_template(SimReaderRegisterInterface())
toplevel_file = "hardware/hdl/vhdl/sim/as_sim_file_reader.vhd"
module.files = []
module.dependencies = ["as_sim_ram_pkg", "helpers"]
module.show_in_browser = True
module.dev_status = AsModule.DevStatus.STABLE
module.module_type = AsModule.ModuleTypes.HARDWARE_SOFTWARE
module.module_category = "Simulation Resources"
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
module.driver_files = [
"hardware/hdl/vhdl/sim/read_byte.h",
"hardware/hdl/vhdl/sim/read_byte.c",
]
return module
