def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
module.add_local_interface_template(AXIMasterExternal())
toplevel_file = "hardware/hdl/vhdl/AXI/AXI_Master.vhd"
module.files = []
module.dependencies = []
module.show_in_browser = True
module.dev_status = AsModule.DevStatus.STABLE
module.module_type = AsModule.ModuleTypes.HARDWARE
module.module_category = "IO Infrastructure"
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
internal_memory = module.get_interface("out")
internal_memory.to_external = False
internal_memory.instantiate_in_top = None
module.get_generic("C_M_AXI_DATA_WIDTH").set_value(None)
module.get_generic("C_M_AXI_ADDR_WIDTH").set_value(None)
module.brief_description = "AXI Master interface. Usually automatically inserted by Automatics. Contains Xilinx-specific HDL code!"
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
toplevel_file = "hardware/hdl/vhdl/as_canny_pipeline.vhd"
module.files = []
module.dependencies = [
"as_regmgr",
"as_generic_filter_module",
"as_pipeline_flush",
"as_edge_threshold",
"as_edge_nms",
"as_cordic_direction",
"as_gradient_weight",
"as_edge_list",
"as_feature_counter",
"helpers",
"as_2d_conv_filter_internal",
"as_pipeline_row",
"as_window_pipeline_helper",
]
module.show_in_browser = True
module.dev_status = AsModule.DevStatus.BETA
module.module_type = AsModule.ModuleTypes.HARDWARE_SW_CTRL
module.module_category = "Image Processing Pipeline"
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
toplevel_file = "hardware/hdl/vhdl/as_sensor_ov7670.vhd"
module.files = []
module.dependencies = ["as_regmgr"]
module.show_in_browser = True
module.dev_status = AsModule.DevStatus.STABLE
module.module_type = AsModule.ModuleTypes.HARDWARE_SW_CTRL
module.module_category = "External IO"
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
module.iic_masters = []
module.iic_masters_available = ("XILINX_PL_IIC", "XILINX_PS_IIC", "AS_IIC")
# Special function definitions for as_sensor_ov7670 module:
def add_iic_master(self, iic_type: str):
self.iic_masters.append(iic_type)
LOG.info("Added IIC master '%s' to '%s'", iic_type, self.name)
def set_iic_masters(self, iic_types: list):
self.iic_masters = iic_types
def list_iic_masters(self):
print("IIC masters available for '{}':".format(self.name))
for iic in self.iic_masters_available:
print(" - '{}'".format(iic))
print("")
def overwrite_sw_additions(self) -> list:
additions = []
for master in self.iic_masters:
additions.append("#define AS_USING_{}".format(master.upper()))
return additions
# Assign functions to module instance
# The call to "__get__(module)" is necessary and "binds" the method
# the instance AsModule instance "module" that was created here!
# Syntax:
# module.<function_name (user script)> = <function to add>.__get__(module)
module.set_iic_masters = set_iic_masters.__get__(module)
module.add_iic_master = add_iic_master.__get__(module)
module.list_iic_masters = list_iic_masters.__get__(module)
module.get_software_additions = overwrite_sw_additions.__get__(module)
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
toplevel_file = "hardware/hdl/vhdl/as_stream_adapter.vhd"
module.files = []
module.dependencies = ["helpers"]
module.dev_status = AsModule.DevStatus.BETA
module.module_type = AsModule.ModuleTypes.HARDWARE_SW_CTRL
module.module_category = "As Stream Infrastructure"
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
toplevel_file = "hardware/hdl/vhdl/as_pixel_conv.vhd"
module.dependencies = []
module.show_in_browser = True
module.dev_status = AsModule.DevStatus.STABLE
module.module_type = AsModule.ModuleTypes.HARDWARE
module.module_category = "Image Processing Operations"
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
toplevel_file = "hardware/hdl/vhdl/fifo/fifo_fwft.vhd"
module.files = []
module.dependencies = ["helpers", "ram"]
module.show_in_browser = False
module.dev_status = AsModule.DevStatus.STABLE
module.module_type = AsModule.ModuleTypes.HARDWARE
module.module_category = "Internal Submodules"
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
return module
def get_module_instance(module_dir):
module = AsModule()
toplevel_file = "hardware/hdl/vhdl/as_base_registers.vhd"
module.dependencies = ["as_regmgr"]
module.show_in_browser = False
module.dev_status = AsModule.DevStatus.WORK_IN_PROGRESS
module.module_type = AsModule.ModuleTypes.HARDWARE_SW_CTRL
module.module_category = "ASTERICS Infrastructure"
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
toplevel_file = "hardware/hdl/vhdl/as_channel_splitter_3.vhd"
module.files = []
module.dependencies = []
module.show_in_browser = True
module.dev_status = AsModule.DevStatus.STABLE
module.module_type = AsModule.ModuleTypes.HARDWARE
module.module_category = "As Stream Infrastructure"
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
toplevel_file = "hardware/hdl/vhdl/as_stream_strobe_counter.vhd"
module.files = []
module.dependencies = []
module.show_in_browser = True
module.dev_status = AsModule.DevStatus.BETA
module.module_type = AsModule.ModuleTypes.HARDWARE_SW_CTRL
module.module_category = "Debugging Modules"
# Automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
toplevel_file = "hardware/hdl/vhdl/as_picam.vhd"
module.files = []
module.dependencies = ["as_regmgr"]
module.show_in_browser = True
module.dev_status = AsModule.DevStatus.ALPHA
module.module_type = AsModule.ModuleTypes.HARDWARE_SW_CTRL
module.module_category = "External IO"
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
toplevel_file = "hardware/hdl/vhdl/as_memwriter.vhd"
module.files = ["hardware/hdl/vhdl/as_mem_address_generator.vhd"]
module.dependencies = ["as_regmgr", "helpers", "fifo_fwft"]
module.show_in_browser = True
module.dev_status = AsModule.DevStatus.STABLE
module.module_type = AsModule.ModuleTypes.HARDWARE_SW_CTRL
module.module_category = "Memory IO"
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
module.add_local_interface_template(SWRegInterface())
toplevel_file = "hardware/hdl/vhdl/register_interface/as_regmgr.vhd"
module.files = [("hardware/hdl/vhdl/register_interface/"
"as_generic_regslice.vhd")]
module.dependencies = ["helpers"]
module.show_in_browser = False
module.dev_status = AsModule.DevStatus.STABLE
module.module_type = AsModule.ModuleTypes.HARDWARE
module.module_category = "Internal Submodules"
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
# Configuration method. This method is automatically executed
# by Automatics during the connection process, only if the module was
# automatically instantiated.
# This way we can access information only available at runtime.
def auto_inst_config(mod, inst_from):
# inst_from is the module that automatically instantiated this module
# mod is the instance of this module that was automatically instantiated
mod.set_generic_value("REG_ADDR_WIDTH", "c_slave_reg_addr_width")
mod.set_generic_value("REG_DATA_WIDTH", "C_S_AXI_DATA_WIDTH")
mod.set_generic_value("MODULE_ADDR_WIDTH", "c_module_addr_width")
base_addr_generic = vstatic.REGMGR_BASEADDR_VAL.format(inst_from.name)
mod.set_generic_value("MODULE_BASEADDR", base_addr_generic)
regmgr_count = "_" + mod.name[-1] if mod.name[-1].isdigit() else ""
target = vstatic.REGMGR_SW_DATA_OUT_TARGET.format(
inst_from.name, regmgr_count)
mod.set_port_fixed_value("sw_data_out", target)
if not regmgr_count:
regif = inst_from.register_ifs[0]
else:
regif = inst_from.register_ifs[int(regmgr_count.strip("_"))]
mod.set_generic_value("REG_COUNT", str(regif.get_reg_count()))
mod.get_interface("out",
if_type="slv_reg_interface").to_external = False
# !Important! Assign the configuration function to this module instance
module.auto_inst_config = auto_inst_config
# Return the module instance to Automatics
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
toplevel_file = "hardware/hdl/vhdl/as_single_conv_filter.vhd"
module.dependencies = [
"as_regmgr",
"as_window_buff_nxm",
"as_generic_filter_module",
"as_pipeline_flush",
]
module.show_in_browser = True
module.dev_status = AsModule.DevStatus.UNMAINTAINED
module.module_type = AsModule.ModuleTypes.HARDWARE_SW_CTRL
module.module_category = "Image Processing Operations"
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
module.files = ["hardware/hdl/vhdl/pkg/helpers.vhd"]
module.dependencies = []
# As this is not a typical Automatics module (no VHDL entity)
# we manually set the necessary attributes,
# so Automatics can work with it normally
module.module_dir = module_dir
module.repository_name = "default"
module.name = ""
module.entity_name = "helpers"
module.generics = []
module.standard_ports = []
module.ports = []
module.interfaces = []
module.show_in_browser = False
module.dev_status = AsModule.DevStatus.STABLE
module.module_type = AsModule.ModuleTypes.LIBRARY
module.module_category = "Internal Libraries"
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
module.files = []
module.dependencies = []
# As this is not a typical Automatics module (no HW files)
# we manually set the necessary attributes,
# so Automatics can work with it
module.module_dir = module_dir
module.repository_name = "default"
module.name = "as_memio"
module.entity_name = "as_memio"
module.generics = []
module.standard_ports = []
module.ports = []
module.interfaces = []
module.show_in_browser = False
module.dev_status = AsModule.DevStatus.BETA
module.module_type = AsModule.ModuleTypes.SOFTWARE
module.module_category = "Memory IO"
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
module.add_local_interface_template(SimReaderRegisterInterface())
toplevel_file = "hardware/hdl/vhdl/sim/as_sim_file_reader.vhd"
module.files = []
module.dependencies = ["as_sim_ram_pkg", "helpers"]
module.show_in_browser = True
module.dev_status = AsModule.DevStatus.STABLE
module.module_type = AsModule.ModuleTypes.HARDWARE_SOFTWARE
module.module_category = "Simulation Resources"
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
module.driver_files = [
"hardware/hdl/vhdl/sim/read_byte.h",
"hardware/hdl/vhdl/sim/read_byte.c",
]
return module
def get_module_instance(module_dir: str) -> AsModule:
module = AsModule()
module.add_local_interface_template(AXISlaveExternal())
toplevel_file = "hardware/hdl/vhdl/AXI/AXI_Slave.vhd"
module.files = []
module.dependencies = ["fifo_fwft", "helpers"]
module.show_in_browser = True
module.dev_status = AsModule.DevStatus.STABLE
module.module_type = AsModule.ModuleTypes.HARDWARE
module.module_category = "IO Infrastructure"
# as_automatics now automatically parses the toplevel file and discovers
# ports, generics, existing interfaces and register interfaces
module.discover_module(module_dir + "/" + toplevel_file)
module.get_generic("C_S_AXI_DATA_WIDTH").set_value(None)
module.get_generic("C_S_AXI_ADDR_WIDTH").set_value(None)
module.brief_description = (
"AXI Slave interface. Usually automatically inserted by Automatics.")
return module
