def main():
parser = argparse.ArgumentParser(epilog=__doc__)
HMC.add_options(parser)
parser.add_argument("commands_to_run",
metavar="command(s)",
nargs='*',
help="Command(s) to run")
parser.add_argument("--cpu",
type=str,
choices=cpu_types.keys(),
default="atomic",
help="CPU model to use")
parser.add_argument("--cpu-freq", type=str, default="4GHz")
parser.add_argument("--num-cores",
type=int,
default=1,
help="Number of CPU cores")
# parser.add_argument("--mem-type", default="DDR3_1600_8x8",
# choices=MemConfig.mem_names(),
# help = "type of memory to use")
# parser.add_argument("--mem-channels", type=int, default=2,
# help = "number of memory channels")
# parser.add_argument("--mem-ranks", type=int, default=None,
# help = "number of memory ranks per channel")
parser.add_argument("--mem-size",
action="store",
type=str,
default="2GB",
help="Specify the physical memory size")
args = parser.parse_args()
# Create a single root node for gem5's object hierarchy. There can
# only exist one root node in the simulator at any given
# time. Tell gem5 that we want to use syscall emulation mode
# instead of full system mode.
root = Root(full_system=False)
# Populate the root node with a system. A system corresponds to a
# single node with shared memory.
root.system = create(args)
# Instantiate the C++ object hierarchy. After this point,
# SimObjects can't be instantiated anymore.
m5.instantiate()
# Start the simulator. This gives control to the C++ world and
# starts the simulator. The returned event tells the simulation
# script why the simulator exited.
event = m5.simulate()
# Print the reason for the simulation exit. Some exit codes are
# requests for service (e.g., checkpoints) from the simulation
# script. We'll just ignore them here and exit.
print(event.getCause(), " @ ", m5.curTick())
sys.exit(event.getCode())
def main():
parser = argparse.ArgumentParser(description="Simple system using HMC as\
main memory")
HMC.add_options(parser)
add_options(parser)
options = parser.parse_args()
# build the system
root = build_system(options)
# instantiate all of the objects we've created so far
m5.instantiate()
print("Beginning simulation!")
event = m5.simulate(10000000000)
m5.stats.dump()
print('Exiting @ tick %i because %s (exit code is %i)' %
(m5.curTick(), event.getCause(), event.getCode()))
print("Done")
def main():
parser = argparse.ArgumentParser(description="Simple system using HMC as\
main memory")
HMC.add_options(parser)
add_options(parser)
options = parser.parse_args()
# build the system
root = build_system(options)
# instantiate all of the objects we've created so far
m5.instantiate()
print("Beginning simulation!")
event = m5.simulate(10000000000)
m5.stats.dump()
print('Exiting @ tick %i because %s (exit code is %i)' % (m5.curTick(),
event.getCause(),
event.getCode()))
print("Done")
def config_mem(options, system):
"""
Create the memory controllers based on the options and attach them.
If requested, we make a multi-channel configuration of the
selected memory controller class by creating multiple instances of
the specific class. The individual controllers have their
parameters set such that the address range is interleaved between
them.
"""
# Mandatory options
opt_mem_channels = options.mem_channels
# Semi-optional options
# Must have either mem_type or nvm_type or both
opt_mem_type = getattr(options, "mem_type", None)
opt_nvm_type = getattr(options, "nvm_type", None)
if not opt_mem_type and not opt_nvm_type:
fatal("Must have option for either mem-type or nvm-type, or both")
# Optional options
opt_tlm_memory = getattr(options, "tlm_memory", None)
opt_external_memory_system = getattr(options, "external_memory_system",
None)
opt_elastic_trace_en = getattr(options, "elastic_trace_en", False)
opt_mem_ranks = getattr(options, "mem_ranks", None)
opt_nvm_ranks = getattr(options, "nvm_ranks", None)
opt_hybrid_channel = getattr(options, "hybrid_channel", False)
opt_dram_powerdown = getattr(options, "enable_dram_powerdown", None)
opt_mem_channels_intlv = getattr(options, "mem_channels_intlv", 128)
opt_xor_low_bit = getattr(options, "xor_low_bit", 0)
if opt_mem_type == "HMC_2500_1x32":
HMChost = HMC.config_hmc_host_ctrl(options, system)
HMC.config_hmc_dev(options, system, HMChost.hmc_host)
subsystem = system.hmc_dev
xbar = system.hmc_dev.xbar
else:
subsystem = system
xbar = system.membus
if opt_tlm_memory:
system.external_memory = m5.objects.ExternalSlave(
port_type="tlm_slave",
port_data=opt_tlm_memory,
port=system.membus.master,
addr_ranges=system.mem_ranges)
system.workload.addr_check = False
return
if opt_external_memory_system:
subsystem.external_memory = m5.objects.ExternalSlave(
port_type=opt_external_memory_system,
port_data="init_mem0", port=xbar.master,
addr_ranges=system.mem_ranges)
subsystem.workload.addr_check = False
return
nbr_mem_ctrls = opt_mem_channels
import math
from m5.util import fatal
intlv_bits = int(math.log(nbr_mem_ctrls, 2))
if 2 ** intlv_bits != nbr_mem_ctrls:
fatal("Number of memory channels must be a power of 2")
if opt_mem_type:
intf = ObjectList.mem_list.get(opt_mem_type)
if opt_nvm_type:
n_intf = ObjectList.mem_list.get(opt_nvm_type)
nvm_intfs = []
mem_ctrls = []
if opt_elastic_trace_en and not issubclass(intf, m5.objects.SimpleMemory):
fatal("When elastic trace is enabled, configure mem-type as "
"simple-mem.")
# The default behaviour is to interleave memory channels on 128
# byte granularity, or cache line granularity if larger than 128
# byte. This value is based on the locality seen across a large
# range of workloads.
intlv_size = max(opt_mem_channels_intlv, system.cache_line_size.value)
# For every range (most systems will only have one), create an
# array of memory interfaces and set their parameters to match
# their address mapping in the case of a DRAM
range_iter = 0
for r in system.mem_ranges:
# As the loops iterates across ranges, assign them alternatively
# to DRAM and NVM if both configured, starting with DRAM
range_iter += 1
for i in range(nbr_mem_ctrls):
if opt_mem_type and (not opt_nvm_type or range_iter % 2 != 0):
# Create the DRAM interface
dram_intf = create_mem_intf(intf, r, i, nbr_mem_ctrls,
intlv_bits, intlv_size, opt_xor_low_bit)
# Set the number of ranks based on the command-line
# options if it was explicitly set
if issubclass(intf, m5.objects.DRAMInterface) and \
opt_mem_ranks:
dram_intf.ranks_per_channel = opt_mem_ranks
# Enable low-power DRAM states if option is set
if issubclass(intf, m5.objects.DRAMInterface):
dram_intf.enable_dram_powerdown = opt_dram_powerdown
if opt_elastic_trace_en:
dram_intf.latency = '1ns'
print("For elastic trace, over-riding Simple Memory "
"latency to 1ns.")
# Create the controller that will drive the interface
if opt_mem_type == "HMC_2500_1x32":
# The static latency of the vault controllers is estimated
# to be smaller than a full DRAM channel controller
mem_ctrl = m5.objects.MemCtrl(min_writes_per_switch = 8,
static_backend_latency = '4ns',
static_frontend_latency = '4ns')
elif opt_mem_type == "SimpleMemory":
mem_ctrl = m5.objects.SimpleMemory()
else:
mem_ctrl = m5.objects.MemCtrl()
# Hookup the controller to the interface and add to the list
if opt_mem_type != "SimpleMemory":
mem_ctrl.dram = dram_intf
mem_ctrls.append(mem_ctrl)
elif opt_nvm_type and (not opt_mem_type or range_iter % 2 == 0):
nvm_intf = create_mem_intf(n_intf, r, i, nbr_mem_ctrls,
intlv_bits, intlv_size)
# Set the number of ranks based on the command-line
# options if it was explicitly set
if issubclass(n_intf, m5.objects.NVMInterface) and \
opt_nvm_ranks:
nvm_intf.ranks_per_channel = opt_nvm_ranks
# Create a controller if not sharing a channel with DRAM
# in which case the controller has already been created
if not opt_hybrid_channel:
mem_ctrl = m5.objects.MemCtrl()
mem_ctrl.nvm = nvm_intf
mem_ctrls.append(mem_ctrl)
else:
nvm_intfs.append(nvm_intf)
# hook up NVM interface when channel is shared with DRAM + NVM
for i in range(len(nvm_intfs)):
mem_ctrls[i].nvm = nvm_intfs[i];
# Connect the controller to the xbar port
for i in range(len(mem_ctrls)):
if opt_mem_type == "HMC_2500_1x32":
# Connect the controllers to the membus
mem_ctrls[i].port = xbar[i/4].master
# Set memory device size. There is an independent controller
# for each vault. All vaults are same size.
mem_ctrls[i].dram.device_size = options.hmc_dev_vault_size
else:
# Connect the controllers to the membus
mem_ctrls[i].port = xbar.master
subsystem.mem_ctrls = mem_ctrls
# Author: Éder F. Zulian
import sys
import argparse
import m5
from m5.objects import *
from m5.util import *
addToPath('../')
from common import MemConfig
from common import HMC
pd = "Simple 'hello world' example using HMC as main memory"
parser = argparse.ArgumentParser(description=pd)
HMC.add_options(parser)
options = parser.parse_args()
# create the system we are going to simulate
system = System()
# use timing mode for the interaction between master-slave ports
system.mem_mode = 'timing'
# set the clock fequency of the system
clk = '1GHz'
vd = VoltageDomain(voltage='1V')
system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
# create a simple CPU
system.cpu = TimingSimpleCPU()
# config memory system
MemConfig.config_mem(options, system)
# hook the CPU ports up to the membus
system.cpu.icache_port = system.membus.slave
def config_mem(options, system):
"""
Create the memory controllers based on the options and attach them.
If requested, we make a multi-channel configuration of the
selected memory controller class by creating multiple instances of
the specific class. The individual controllers have their
parameters set such that the address range is interleaved between
them.
"""
# Mandatory options
opt_mem_type = options.mem_type
opt_mem_channels = options.mem_channels
# Optional options
opt_tlm_memory = getattr(options, "tlm_memory", None)
opt_external_memory_system = getattr(options, "external_memory_system",
None)
opt_elastic_trace_en = getattr(options, "elastic_trace_en", False)
opt_mem_ranks = getattr(options, "mem_ranks", None)
opt_dram_powerdown = getattr(options, "enable_dram_powerdown", None)
opt_mem_channels_intlv = getattr(options, "mem_channels_intlv", 128)
if opt_mem_type == "HMC_2500_1x32":
HMChost = HMC.config_hmc_host_ctrl(options, system)
HMC.config_hmc_dev(options, system, HMChost.hmc_host)
subsystem = system.hmc_dev
xbar = system.hmc_dev.xbar
else:
subsystem = system
xbar = system.membus
if opt_tlm_memory:
system.external_memory = m5.objects.ExternalSlave(
port_type="tlm_slave",
port_data=opt_tlm_memory,
port=system.membus.master,
addr_ranges=system.mem_ranges)
system.workload.addr_check = False
return
if opt_external_memory_system:
subsystem.external_memory = m5.objects.ExternalSlave(
port_type=opt_external_memory_system,
port_data="init_mem0",
port=xbar.master,
addr_ranges=system.mem_ranges)
subsystem.workload.addr_check = False
return
nbr_mem_ctrls = opt_mem_channels
import math
from m5.util import fatal
intlv_bits = int(math.log(nbr_mem_ctrls, 2))
if 2**intlv_bits != nbr_mem_ctrls:
fatal("Number of memory channels must be a power of 2")
cls = ObjectList.mem_list.get(opt_mem_type)
mem_ctrls = []
if opt_elastic_trace_en and not issubclass(cls, m5.objects.SimpleMemory):
fatal("When elastic trace is enabled, configure mem-type as "
"simple-mem.")
# The default behaviour is to interleave memory channels on 128
# byte granularity, or cache line granularity if larger than 128
# byte. This value is based on the locality seen across a large
# range of workloads.
intlv_size = max(opt_mem_channels_intlv, system.cache_line_size.value)
# For every range (most systems will only have one), create an
# array of controllers and set their parameters to match their
# address mapping in the case of a DRAM
for r in system.mem_ranges:
for i in range(nbr_mem_ctrls):
mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits,
intlv_size)
# Set the number of ranks based on the command-line
# options if it was explicitly set
if issubclass(cls, m5.objects.DRAMCtrl) and opt_mem_ranks:
mem_ctrl.ranks_per_channel = opt_mem_ranks
# Enable low-power DRAM states if option is set
if issubclass(cls, m5.objects.DRAMCtrl):
mem_ctrl.enable_dram_powerdown = opt_dram_powerdown
if opt_elastic_trace_en:
mem_ctrl.latency = '1ns'
print("For elastic trace, over-riding Simple Memory "
"latency to 1ns.")
mem_ctrls.append(mem_ctrl)
subsystem.mem_ctrls = mem_ctrls
# Connect the controllers to the membus
for i in range(len(subsystem.mem_ctrls)):
if opt_mem_type == "HMC_2500_1x32":
subsystem.mem_ctrls[i].port = xbar[i / 4].master
# Set memory device size. There is an independent controller for
# each vault. All vaults are same size.
subsystem.mem_ctrls[i].device_size = options.hmc_dev_vault_size
else:
subsystem.mem_ctrls[i].port = xbar.master
# Author: Éder F. Zulian
import sys
import argparse
import m5
from m5.objects import *
from m5.util import *
addToPath('../')
from common import MemConfig
from common import HMC
pd = "Simple 'hello world' example using HMC as main memory"
parser = argparse.ArgumentParser(description=pd)
HMC.add_options(parser)
options = parser.parse_args()
# create the system we are going to simulate
system = System()
# use timing mode for the interaction between master-slave ports
system.mem_mode = 'timing'
# set the clock fequency of the system
clk = '1GHz'
vd = VoltageDomain(voltage='1V')
system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
# create a simple CPU
system.cpu = TimingSimpleCPU()
# config memory system
MemConfig.config_mem(options, system)
# hook the CPU ports up to the membus
system.cpu.icache_port = system.membus.slave