def gen_wrapper(params: GlobalControllerParams = None):
type_map = {
"clk_in": magma.In(magma.Clock),
"clk_out": magma.Out(magma.Clock),
"tck": magma.In(magma.Clock),
"reset_in": magma.In(magma.AsyncReset),
"reset_out": magma.Out(magma.AsyncReset),
"trst_n": magma.In(magma.AsyncReset),
}
interface = GeneratorInterface()
if params is not None:
genesis_params = dataclasses.asdict(params)
for k, v in genesis_params.items():
interface = interface.register(k, int, v)
gc_wrapper = GenesisWrapper(interface,
"global_controller",
["global_controller/rtl/genesis/global_controller.svp",
"global_controller/rtl/genesis/jtag.svp",
"global_controller/rtl/genesis/glc_axi_ctrl.svp",
"global_controller/rtl/genesis/glc_axi_addrmap.svp",
"global_controller/rtl/genesis/glc_jtag_ctrl.svp",
"global_controller/rtl/genesis/tap.svp",
"global_controller/rtl/genesis/flop.svp",
"global_controller/rtl/genesis/cfg_and_dbg.svp"],
system_verilog=True, type_map=type_map)
return gc_wrapper
interface = GeneratorInterface()\
.register("data_depth", int, 128)\
.register("num_banks", int, 2)\
.register("data_width", int, 64)\
.register("word_width", int, 16)\
.register("use_sram_stub", int, 1)
memory_core_wrapper = GenesisWrapper(
interface,
"memory_core", [
"memory_core/genesis_new/linebuffer_control.svp",
"memory_core/genesis_new/fifo_control.svp",
"memory_core/genesis_new/doublebuffer_control.svp",
"memory_core/genesis_new/mem.vp",
"memory_core/genesis_new/sram_control.svp",
"memory_core/genesis_new/memory_core.svp",
"memory_core/genesis_new/sram_stub.vp"
],
type_map={
"clk": m.In(m.Clock),
"reset": m.In(m.AsyncReset),
"config_en": m.In(m.Enable)
},
system_verilog=True)
param_mapping = {
"data_width": "dwidth",
"data_depth": "ddepth",
"word_width": "wwidth",
"num_banks": "bbanks",
"use_sram_stub": "use_sram_stub"
"num_io": "num_io_channels",
"num_cfg": "num_cfg_channels",
"bank_addr": "bank_addr_width",
"cfg_addr": "config_addr_width",
"cfg_data": "config_data_width"
}
glb_wrapper = GenesisWrapper(
interface,
"global_buffer", [
"global_buffer/genesis/global_buffer.svp",
"global_buffer/genesis/global_buffer_int.svp",
"global_buffer/genesis/memory_bank.svp",
"global_buffer/genesis/cfg_bank_interconnect.svp",
"global_buffer/genesis/bank_controller.svp",
"global_buffer/genesis/host_bank_interconnect.svp",
"global_buffer/genesis/addrgen_bank_interconnect.svp",
"global_buffer/genesis/address_generator.svp",
"global_buffer/genesis/glbuf_memory_core.svp",
"global_buffer/genesis/memory.svp",
"global_buffer/genesis/sram_gen.svp",
"global_buffer/genesis/sram_controller.svp"
],
system_verilog=True,
type_map=type_map)
if __name__ == "__main__":
"""
This program generates the verilog for the global buffer and parses
it into a Magma circuit. The circuit declaration is printed at the
end of the program.
"""
import pytest
import inspect
import random
import magma as m
from gemstone.common.genesis_wrapper import GenesisWrapper
from gemstone.common.generator_interface import GeneratorInterface
TOP = "test_run_genesis"
INFILES = ["tests/common/test_run_genesis.vp"]
PARAMS = {
"width": 16,
}
INTERFACE = GeneratorInterface()\
.register("width", int, 32)
WRAPPER = GenesisWrapper(INTERFACE, TOP, INFILES)
@pytest.mark.parametrize("mode", ["declare", "define"])
def test_generator(mode):
def _foo(*args, **kwargs):
pass
generator = WRAPPER.generator(mode=mode)
assert inspect.isfunction(generator)
assert inspect.signature(generator) == inspect.signature(_foo)
# Check that passing non-kwargs fails.
try:
generator(0)
assert False
except NotImplementedError as e:
pass
.register("cfg_addr_width", int, 32)\
.register("cfg_op_width", int, 5)\
.register("axi_addr_width", int, 12)
type_map = {
"clk_in": magma.In(magma.Clock),
"clk_out": magma.Out(magma.Clock),
"tck": magma.In(magma.Clock),
"reset_in": magma.In(magma.AsyncReset),
"reset_out": magma.Out(magma.AsyncReset),
"trst_n": magma.In(magma.AsyncReset),
}
gc_wrapper = GenesisWrapper(interface,
"global_controller",
["global_controller/genesis/global_controller.svp",
"global_controller/genesis/jtag.svp",
"global_controller/genesis/axi_ctrl.svp",
"global_controller/genesis/tap.svp",
"global_controller/genesis/flop.svp",
"global_controller/genesis/cfg_and_dbg.svp"],
system_verilog=True, type_map=type_map)
if __name__ == "__main__":
"""
This program generates the verilog for the global controller and parses it
into a Magma circuit. The circuit declaration is printed at the end of the
program.
"""
# These functions are unit tested directly, so no need to cover them
gc_wrapper.main() # pragma: no cover
`data_width`: width of an entry in the memory
`data_depth`: number of entries in the memory
Example usage:
>>> memory_core = memory_core_wrapper.generator()(
data_width=16, data_depth=1024)
"""
interface = GeneratorInterface()\
.register("data_width", int, 16)\
.register("data_depth", int, 1024)
memory_core_wrapper = GenesisWrapper(
interface, "memory_core", ["memory_core/genesis/input_sr.vp",
"memory_core/genesis/output_sr.vp",
"memory_core/genesis/linebuffer_control.vp",
"memory_core/genesis/fifo_control.vp",
"memory_core/genesis/mem.vp",
"memory_core/genesis/memory_core.vp"],
type_map={"clk_in": m.In(m.Clock),
"reset": m.In(m.AsyncReset),
"config_en": m.In(m.Enable)})
param_mapping = {"data_width": "dwidth", "data_depth": "ddepth"}
if __name__ == "__main__":
"""
This program generates the verilog for the memory core and parses it into a
Magma circuit. The circuit declaration is printed at the end of the
program.
"""
# These functions are unit tested directly, so no need to cover them
memory_core_wrapper.main(param_mapping=param_mapping) # pragma: no cover