"cfg_data": "config_data_width"
}
glb_wrapper = GenesisWrapper(
interface,
"global_buffer", [
"global_buffer/genesis/global_buffer.svp",
"global_buffer/genesis/global_buffer_int.svp",
"global_buffer/genesis/memory_bank.svp",
"global_buffer/genesis/cfg_bank_interconnect.svp",
"global_buffer/genesis/bank_controller.svp",
"global_buffer/genesis/host_bank_interconnect.svp",
"global_buffer/genesis/addrgen_bank_interconnect.svp",
"global_buffer/genesis/address_generator.svp",
"global_buffer/genesis/glbuf_memory_core.svp",
"global_buffer/genesis/memory.svp",
"global_buffer/genesis/sram_gen.svp",
"global_buffer/genesis/sram_controller.svp"
],
system_verilog=True,
type_map=type_map)
if __name__ == "__main__":
"""
This program generates the verilog for the global buffer and parses
it into a Magma circuit. The circuit declaration is printed at the
end of the program.
"""
# These functions are unit tested directly, so no need to cover them
glb_wrapper.main(param_mapping=param_mapping) # pragma: no cover
"memory_core/genesis_new/fifo_control.svp",
"memory_core/genesis_new/doublebuffer_control.svp",
"memory_core/genesis_new/mem.vp",
"memory_core/genesis_new/sram_control.svp",
"memory_core/genesis_new/memory_core.svp",
"memory_core/genesis_new/sram_stub.vp"
],
type_map={
"clk": m.In(m.Clock),
"reset": m.In(m.AsyncReset),
"config_en": m.In(m.Enable)
},
system_verilog=True)
param_mapping = {
"data_width": "dwidth",
"data_depth": "ddepth",
"word_width": "wwidth",
"num_banks": "bbanks",
"use_sram_stub": "use_sram_stub"
}
if __name__ == "__main__":
"""
This program generates the verilog for the memory core and parses it into a
Magma circuit. The circuit declaration is printed at the end of the
program.
"""
# These functions are unit tested directly, so no need to cover them
memory_core_wrapper.main(param_mapping=param_mapping) # pragma: no cover
.register("cfg_addr_width", int, 32)\
.register("cfg_op_width", int, 5)\
.register("axi_addr_width", int, 12)
type_map = {
"clk_in": magma.In(magma.Clock),
"clk_out": magma.Out(magma.Clock),
"tck": magma.In(magma.Clock),
"reset_in": magma.In(magma.AsyncReset),
"reset_out": magma.Out(magma.AsyncReset),
"trst_n": magma.In(magma.AsyncReset),
}
gc_wrapper = GenesisWrapper(interface,
"global_controller",
["global_controller/genesis/global_controller.svp",
"global_controller/genesis/jtag.svp",
"global_controller/genesis/axi_ctrl.svp",
"global_controller/genesis/tap.svp",
"global_controller/genesis/flop.svp",
"global_controller/genesis/cfg_and_dbg.svp"],
system_verilog=True, type_map=type_map)
if __name__ == "__main__":
"""
This program generates the verilog for the global controller and parses it
into a Magma circuit. The circuit declaration is printed at the end of the
program.
"""
# These functions are unit tested directly, so no need to cover them
gc_wrapper.main() # pragma: no cover