def main(): dut = Refresher(13, 2, tRP=3, tREFI=100, tRFC=5) logger = CommandLogger(dut.cmd) granter = Granter(dut.req, dut.ack) fragment = dut.get_fragment() + logger.get_fragment() + granter.get_fragment() sim = Simulator(fragment) sim.run(400)
def main():
# Create graph
g = DataFlowGraph()
gen1 = ComposableSource(g, NumberGen())
gen2 = ComposableSource(g, NumberGen())
ps = gen1 + gen2
result = ps*gen1 + ps*gen2
g.add_connection(result.actor_node, ActorNode(Dumper()))
gen1.actor_node.actor.name = "gen1"
gen2.actor_node.actor.name = "gen2"
result.actor_node.name = "result"
# Elaborate
print("is_abstract before elaboration: " + str(g.is_abstract()))
draw(g)
g.elaborate()
print("is_abstract after elaboration : " + str(g.is_abstract()))
draw(g)
# Simulate
c = CompositeActor(g)
fragment = c.get_fragment()
sim = Simulator(fragment, Runner())
sim.run(100)
def main():
# Compute filter coefficients with SciPy.
coef = signal.remez(80, [0, 0.1, 0.1, 0.5], [1, 0])
fir = FIR(coef)
# Simulate for different frequencies and concatenate
# the results.
in_signals = []
out_signals = []
for frequency in [0.05, 0.07, 0.1, 0.15, 0.2]:
tb = TB(fir, frequency)
fragment = autofragment.from_local()
sim = Simulator(fragment, Runner())
sim.run(100)
in_signals += tb.inputs
out_signals += tb.outputs
# Plot data from the input and output waveforms.
plt.plot(in_signals)
plt.plot(out_signals)
plt.show()
# Print the Verilog source for the filter.
print(verilog.convert(fir.get_fragment(),
ios={fir.i, fir.o}))
def main(): nbits = 32 # See: # http://www.csse.monash.edu.au/~damian/Idioms/Topics/12.1.DataFlow/html/text.html g = DataFlowGraph() adder = ActorNode(Add(BV(nbits))) bufadd = ActorNode(plumbing.Buffer) # TODO FIXME: deadlocks without this buffer init1 = ActorNode(Init(nbits)) buf1 = ActorNode(plumbing.Buffer) init2 = ActorNode(Init(nbits)) buf2 = ActorNode(plumbing.Buffer) g.add_connection(adder, bufadd) g.add_connection(bufadd, init1) g.add_connection(init1, buf1) g.add_connection(buf1, adder, sink_subr="a") g.add_connection(buf1, init2) g.add_connection(init2, buf2) g.add_connection(buf2, adder, sink_subr="b") g.add_connection(bufadd, ActorNode(Dumper(nbits))) c = CompositeActor(g) fragment = c.get_fragment() sim = Simulator(fragment, Runner()) sim.run(100)
def main(): hub = asmibus.Hub(16, 128) port = hub.get_port() hub.finalize() dut = Framebuffer(1, port, True) fragment = hub.get_fragment() + dut.get_fragment() sim = Simulator(fragment) sim.run(1) def csr_w(addr, d): sim.wr(dut.bank.description[addr].field.storage, d) hres = 4 vres = 4 csr_w(1, hres) # hres csr_w(2, hres+3) # hsync_start csr_w(3, hres+5) # hsync_stop csr_w(4, hres+10) # hscan csr_w(5, vres) # vres csr_w(6, vres+3) # vsync_start csr_w(7, vres+5) # vsync_stop csr_w(8, vres+10) # vscan csr_w(10, hres*vres*4) # length csr_w(0, 1) # enable sim.run(1000)
def main(): dut = Counter() # We do not specify a top-level nor runner object, and use the defaults. sim = Simulator(dut.get_fragment()) # Since we do not use sim.interrupt, limit the simulation # to some number of cycles. sim.run(20)
def main():
base_layout = [("value", 32)]
packed_layout = structuring.pack_layout(base_layout, pack_factor)
rawbits_layout = [("value", 32*pack_factor)]
source = SimActor(source_gen(), ("source", Source, base_layout))
sink = SimActor(sink_gen(), ("sink", Sink, base_layout))
# A tortuous way of passing integer tokens.
packer = structuring.Pack(base_layout, pack_factor)
to_raw = structuring.Cast(packed_layout, rawbits_layout)
from_raw = structuring.Cast(rawbits_layout, packed_layout)
unpacker = structuring.Unpack(pack_factor, base_layout)
g = DataFlowGraph()
g.add_connection(source, packer)
g.add_connection(packer, to_raw)
g.add_connection(to_raw, from_raw)
g.add_connection(from_raw, unpacker)
g.add_connection(unpacker, sink)
comp = CompositeActor(g)
reporter = perftools.DFGReporter(g)
fragment = comp.get_fragment() + reporter.get_fragment()
sim = Simulator(fragment, Runner())
sim.run(1000)
g_layout = nx.spectral_layout(g)
nx.draw(g, g_layout)
nx.draw_networkx_edge_labels(g, g_layout, reporter.get_edge_labels())
plt.show()
def test_writer():
print("*** Testing writer")
trgen = SimActor(trgen_gen(), ("address_data", Source, [("a", BV(30)), ("d", BV(32))]))
writer = dma_wishbone.Writer()
g = DataFlowGraph()
g.add_connection(trgen, writer)
comp = CompositeActor(g)
peripheral = MyPeripheral()
tap = wishbone.Tap(peripheral.bus)
interconnect = wishbone.InterconnectPointToPoint(writer.bus, peripheral.bus)
def end_simulation(s):
s.interrupt = trgen.done and not s.rd(comp.busy)
fragment = (
comp.get_fragment()
+ peripheral.get_fragment()
+ tap.get_fragment()
+ interconnect.get_fragment()
+ Fragment(sim=[end_simulation])
)
sim = Simulator(fragment, Runner())
sim.run()
class SDRAMHostReadTest(sim.sdram_test_util.SDRAMUTFramework, unittest.TestCase):
# def setUp(self):
def _run(self, dummy_data, dummy_idle, max_burst_length, host_burst_length):
self.tb = TestBench("mt48lc16m16a2", dummy_data, dummy_idle, max_burst_length, host_burst_length)
# Verify that all necessary files are present
files = gather_files(self.tb)
for i in files:
if not os.path.exists(i):
raise FileNotFoundError("Please download and save the vendor "
"SDRAM model in %s (not redistributable)"
% i)
runner = icarus.Runner(extra_files=files)
vcd = "test_%s.vcd" % self.__class__.__name__
self.sim = Simulator(self.tb, TopLevel(vcd), sim_runner=runner)
with self.sim:
self.sim.run(10000)
def test_sdram_host_read(self):
self._run(300, 1000, 256, 16)
def test_sdram_host_read_2(self):
self._run(300, 10, 256, 256)
def test_sdram_host_read_3(self):
self._run(300, 1000, 16, 17)
def test_sdram_host_read_4(self):
self._run(300, 10, 32, 64)
def main():
dut = Counter()
# Use the Icarus Verilog runner.
# We do not specify a top-level object, and use the default.
sim = Simulator(dut.get_fragment(), Runner())
# Since we do not use sim.interrupt, limit the simulation
# to some number of cycles.
sim.run(20)
def run_sim(ng): g = DataFlowGraph() d = Dumper(layout) g.add_connection(ng, d) c = CompositeActor(g) sim = Simulator(c) sim.run(30) del sim
def run_sim(ng): g = DataFlowGraph() d = Dumper(layout) g.add_connection(ng, d) c = CompositeActor(g) fragment = c.get_fragment() sim = Simulator(fragment, Runner()) sim.run(30) del sim
def main(): g = DataFlowGraph() g.add_connection(DataGen(), PE43602Driver(PE43602())) c = CompositeActor(g) def end_simulation(s): s.interrupt = s.cycle_counter > 5 and not s.rd(c.busy) f = c.get_fragment() + Fragment(sim=[end_simulation]) sim = Simulator(f, TopLevel(vcd_name="pe43602.vcd")) sim.run()
def main(): source = SimSource() loop = misc.IntSequence(32) sink = SimSink() g = DataFlowGraph() g.add_connection(source, loop) g.add_connection(loop, sink) comp = CompositeActor(g) sim = Simulator(comp) sim.run(500)
def main():
source = SimActor(source_gen(), ("source", Source, [("value", 32)]))
loop = misc.IntSequence(32)
sink = SimActor(sink_gen(), ("sink", Sink, [("value", 32)]))
g = DataFlowGraph()
g.add_connection(source, loop)
g.add_connection(loop, sink)
comp = CompositeActor(g)
fragment = comp.get_fragment()
sim = Simulator(fragment)
sim.run(500)
def main():
source = SimActor(source_gen(), ("source", Source, [("value", 32)]))
sink = SimActor(sink_gen(), ("sink", Sink, [("value", 32)]))
g = DataFlowGraph()
g.add_connection(source, sink)
comp = CompositeActor(g)
def end_simulation(s):
s.interrupt = source.token_exchanger.done
fragment = comp.get_fragment() + Fragment(sim=[end_simulation])
sim = Simulator(fragment, Runner())
sim.run()
def main():
source = ActorNode(SimActor(source_gen(), ("source", Source, [("value", BV(32))])))
loop = ActorNode(control.For(32))
sink = ActorNode(SimActor(sink_gen(), ("sink", Sink, [("value", BV(32))])))
g = DataFlowGraph()
g.add_connection(source, loop)
g.add_connection(loop, sink)
comp = CompositeActor(g)
fragment = comp.get_fragment()
sim = Simulator(fragment, Runner())
sim.run(500)
def main():
source = ActorNode(
SimActor(source_gen(), ("source", Source, [("value", BV(32))])))
loop = ActorNode(control.For(32))
sink = ActorNode(SimActor(sink_gen(), ("sink", Sink, [("value", BV(32))])))
g = DataFlowGraph()
g.add_connection(source, loop)
g.add_connection(loop, sink)
comp = CompositeActor(g)
fragment = comp.get_fragment()
sim = Simulator(fragment, Runner())
sim.run(500)
def _main():
from migen.sim.generic import Simulator, TopLevel
from migen.fhdl import verilog
pads = Record([("cs_n", 1), ("clk", 1), ("dq", 4)])
s = SpiFlash(pads)
print(verilog.convert(s, ios={pads.clk, pads.cs_n, pads.dq, s.bus.adr,
s.bus.dat_r, s.bus.cyc, s.bus.ack, s.bus.stb}))
tb = SpiFlashTB()
sim = Simulator(tb, TopLevel("spiflash.vcd"))
sim.run()
def asmi_sim(efragment, hub, end_simulation): def _end_simulation(s): s.interrupt = end_simulation(s) peripheral = asmibus.Target(hub, MyModelASMI()) tap = asmibus.Tap(hub) def _end_simulation(s): s.interrupt = end_simulation(s) fragment = efragment \ + peripheral.get_fragment() \ + tap.get_fragment() \ + Fragment(sim=[_end_simulation]) sim = Simulator(fragment, Runner()) sim.run()
def wishbone_sim(efragment, master, end_simulation): peripheral = wishbone.Target(MyModelWB()) tap = wishbone.Tap(peripheral.bus) interconnect = wishbone.InterconnectPointToPoint(master.bus, peripheral.bus) def _end_simulation(s): s.interrupt = end_simulation(s) fragment = efragment \ + peripheral.get_fragment() \ + tap.get_fragment() \ + interconnect.get_fragment() \ + Fragment(sim=[_end_simulation]) sim = Simulator(fragment, Runner()) sim.run()
def wishbone_sim(efragment, master, end_simulation): peripheral = wishbone.Target(MyModelWB()) tap = wishbone.Tap(peripheral.bus) interconnect = wishbone.InterconnectPointToPoint(master.bus, peripheral.bus) def _end_simulation(s): s.interrupt = end_simulation(s) fragment = efragment \ + peripheral.get_fragment() \ + tap.get_fragment() \ + interconnect.get_fragment() \ + Fragment(sim=[_end_simulation]) sim = Simulator(fragment) sim.run()
def asmi_sim(efragment, hub, end_simulation): def _end_simulation(s): s.interrupt = end_simulation(s) peripheral = asmibus.Target(MyModelASMI(), hub) tap = asmibus.Tap(hub) def _end_simulation(s): s.interrupt = end_simulation(s) fragment = efragment \ + peripheral.get_fragment() \ + tap.get_fragment() \ + Fragment(sim=[_end_simulation]) sim = Simulator(fragment) sim.run()
def setUp(self):
self.tb = TestBench("mt48lc16m16a2")
# Verify that all necessary files are present
files = gather_files(self.tb)
for i in files:
if not os.path.exists(i):
raise FileNotFoundError("Please download and save the vendor "
"SDRAM model in %s (not redistributable)"
% i)
runner = icarus.Runner(extra_files=files)
vcd = "test_%s.vcd" % self.__class__.__name__
self.sim = Simulator(self.tb, TopLevel(vcd), sim_runner=runner)
def run_sim(ng): g = DataFlowGraph() d = Dumper(layout) g.add_connection(ng, d) slave = wishbone.Target(SlaveModel()) intercon = wishbone.InterconnectPointToPoint(ng.buses["wb"], slave.bus) c = CompositeActor(g) fragment = slave.get_fragment() + intercon.get_fragment() + c.get_fragment() sim = Simulator(fragment) sim.run(50) del sim
def main():
dut = ASMIcon(sdram_phy, sdram_geom, sdram_timing)
initiator1 = Initiator(my_generator_r(), dut.hub.get_port())
initiator2 = Initiator(my_generator_w(), dut.hub.get_port())
dut.finalize()
logger = DFILogger(dut.dfi)
def end_simulation(s):
s.interrupt = initiator1.done and initiator2.done
fragment = dut.get_fragment() + initiator1.get_fragment() + initiator2.get_fragment() + \
logger.get_fragment() + \
Fragment(sim=[end_simulation])
sim = Simulator(fragment, TopLevel("my.vcd"))
sim.run(700)
def run(self):
with Simulator(self) as sim:
sim.run()
w = 2**(self.dut.width - 1)
x = self.x[:-self.dut.latency - 1] / w
y = self.y[self.dut.latency + 1:] / w
return x, y
def test_asmi():
print("*** ASMI test")
# Create a hub with one port for our initiator.
hub = asmibus.Hub(32, 32)
port = hub.get_port()
hub.finalize()
# Create the initiator, target and tap (similar to the Wishbone case).
master = asmibus.Initiator(my_generator(), port)
slave = asmibus.Target(MyModelASMI(), hub)
tap = asmibus.Tap(hub)
# Run the simulation (same as the Wishbone case).
def end_simulation(s):
s.interrupt = master.done
fragment = autofragment.from_local() + Fragment(sim=[end_simulation])
sim = Simulator(fragment)
sim.run()
def main():
hub = Hub(12, 128, 2)
initiator = Initiator(hub.get_port(), my_generator())
hub.finalize()
dut = BankMachine(sdram_geom, sdram_timing, 2, 0, hub.get_slots())
logger = CommandLogger(dut.cmd, True)
completer = Completer(hub, dut.cmd)
def end_simulation(s):
s.interrupt = initiator.done
fragment = hub.get_fragment() + initiator.get_fragment() + \
dut.get_fragment() + logger.get_fragment() + completer.get_fragment() + \
Fragment(sim=[end_simulation])
sim = Simulator(fragment, TopLevel("my.vcd"))
sim.run()
def main(): # The "wishbone.Initiator" library component runs our generator # and manipulates the bus signals accordingly. master = wishbone.Initiator(my_generator()) # Our slave. slave = MyPeripheral() # The "wishbone.Tap" library component examines the bus at the slave port # and displays the transactions on the console (<TRead...>/<TWrite...>). tap = wishbone.Tap(slave.bus) # Connect the master to the slave. intercon = wishbone.InterconnectPointToPoint(master.bus, slave.bus) # A small extra simulation function to terminate the process when # the initiator is done (i.e. our generator is exhausted). def end_simulation(s): s.interrupt = master.done fragment = autofragment.from_local() + Fragment(sim=[end_simulation]) sim = Simulator(fragment, Runner()) sim.run()
def test_asmi():
print("*** ASMI test")
# Create a hub with one port for our initiator.
hub = asmibus.Hub(32, 32)
port = hub.get_port()
hub.finalize()
# Create the initiator, target and tap (similar to the Wishbone case).
master = asmibus.Initiator(port, my_generator())
slave = asmibus.Target(hub, MyModelASMI())
tap = asmibus.Tap(hub)
# Run the simulation (same as the Wishbone case).
def end_simulation(s):
s.interrupt = master.done
fragment = autofragment.from_local() + Fragment(sim=[end_simulation])
sim = Simulator(fragment, Runner())
sim.run()
def main():
hub = Hub(12, 128, 8)
initiators = [Initiator(hub.get_port(), my_generator(0, 2200*(i//6)+i*10))
for i in range(8)]
hub.finalize()
slots = hub.get_slots()
slicer = _AddressSlicer(sdram_geom, 2)
logger = SlotsLogger(slicer, slots)
selector = Selector(slicer, 0, slots)
completer = Completer(hub, selector.queue)
def end_simulation(s):
s.interrupt = all([i.done for i in initiators])
fragment = hub.get_fragment() + sum([i.get_fragment() for i in initiators], Fragment()) + \
logger.get_fragment() + selector.get_fragment() + completer.get_fragment() + \
Fragment(sim=[end_simulation])
sim = Simulator(fragment, TopLevel("my.vcd"))
sim.run()
def _inner_setup(self):
# Verify that all necessary files are present
files = gather_files(self.tb)
for i in files:
if not os.path.exists(i):
raise FileNotFoundError(
"Please download and save the vendor "
"SDRAM model in %s (not redistributable)" % i)
runner = icarus.Runner(extra_files=files)
self.sim = Simulator(self.tb, sim_runner=runner)
def main():
controller = ASMIcon(sdram_phy, sdram_geom, sdram_timing)
bridge = wishbone2asmi.WB2ASMI(l2_size//4, controller.hub.get_port())
controller.finalize()
initiator = wishbone.Initiator(my_generator())
conn = wishbone.InterconnectPointToPoint(initiator.bus, bridge.wishbone)
logger = DFILogger(controller.dfi)
def end_simulation(s):
s.interrupt = initiator.done
fragment = controller.get_fragment() + \
bridge.get_fragment() + \
initiator.get_fragment() + \
conn.get_fragment() + \
logger.get_fragment() + \
Fragment(sim=[end_simulation])
sim = Simulator(fragment, TopLevel("my.vcd"))
sim.run()
def main():
# The "wishbone.Initiator" library component runs our generator
# and manipulates the bus signals accordingly.
master = wishbone.Initiator(my_generator())
# Our slave.
slave = MyPeripheral()
# The "wishbone.Tap" library component examines the bus at the slave port
# and displays the transactions on the console (<TRead...>/<TWrite...>).
tap = wishbone.Tap(slave.bus)
# Connect the master to the slave.
intercon = wishbone.InterconnectPointToPoint(master.bus, slave.bus)
# A small extra simulation function to terminate the process when
# the initiator is done (i.e. our generator is exhausted).
def end_simulation(s):
s.interrupt = master.done
fragment = autofragment.from_local() + Fragment(sim=[end_simulation])
sim = Simulator(fragment, Runner())
sim.run()
class SDRAMSinkTest(sim.sdram_test_util.SDRAMUTFramework, unittest.TestCase):
def setUp(self):
self.tb = TestBench("mt48lc16m16a2")
# Verify that all necessary files are present
files = gather_files(self.tb)
for i in files:
if not os.path.exists(i):
raise FileNotFoundError("Please download and save the vendor "
"SDRAM model in %s (not redistributable)"
% i)
runner = icarus.Runner(extra_files=files)
vcd = "test_%s.vcd" % self.__class__.__name__
self.sim = Simulator(self.tb, TopLevel(vcd), sim_runner=runner)
def _run(self):
with self.sim:
self.sim.run(10000)
def test_sdramsink(self):
self._run()
class SDRAMSinkTest(sim.sdram_test_util.SDRAMUTFramework, unittest.TestCase):
def setUp(self):
self.tb = TestBench("mt48lc16m16a2")
# Verify that all necessary files are present
files = gather_files(self.tb)
for i in files:
if not os.path.exists(i):
raise FileNotFoundError(
"Please download and save the vendor " "SDRAM model in %s (not redistributable)" % i
)
runner = icarus.Runner(extra_files=files)
vcd = "test_%s.vcd" % self.__class__.__name__
self.sim = Simulator(self.tb, TopLevel(vcd), sim_runner=runner)
def _run(self):
with self.sim:
self.sim.run(10000)
def test_sdramsink(self):
self._run()
def main():
# Create a simple dataflow system
receiver_layout = [
("i0", width),
("q0", width),
("i1", width),
("q1", width)
]
wg_i = CSRWG(0, depth, width, 2)
wg_q = CSRWG(0, depth, width, 2)
sink = SimActor(receiver(), ("sample", Sink, receiver_layout))
g = DataFlowGraph()
g.add_connection(wg_i, sink, sink_subr=["i0", "i1"])
g.add_connection(wg_q, sink, sink_subr=["q0", "q1"])
comp = CompositeActor(g)
# CSR programmer and interconnect
csr_i_prog = csr.Initiator(programmer(values_i, received_values_i))
csr_i_intercon = csr.Interconnect(csr_i_prog.bus, [wg_i.bank.bus])
csr_q_prog = csr.Initiator(programmer(values_q, received_values_q))
csr_q_intercon = csr.Interconnect(csr_q_prog.bus, [wg_q.bank.bus])
# Run the simulation until the CSR programmer finishes
def end_simulation(s):
s.interrupt = csr_i_prog.done and csr_q_prog.done
frag = comp.get_fragment() \
+ csr_i_prog.get_fragment() + csr_i_intercon.get_fragment() \
+ csr_q_prog.get_fragment() + csr_q_intercon.get_fragment() \
+ Fragment(sim=[end_simulation])
sim = Simulator(frag)
sim.run()
# Check correctness of the first received values
assert(received_values_i[:depth] == values_i)
assert(received_values_q[:depth] == values_q)
# Plot waveform
plt.plot(received_values_i)
plt.plot(received_values_q)
plt.show()
def setUp(self):
self.tb = TestBench("mt48lc16m16a2")
# Verify that all necessary files are present
files = gather_files(self.tb)
for i in files:
if not os.path.exists(i):
raise FileNotFoundError(
"Please download and save the vendor " "SDRAM model in %s (not redistributable)" % i
)
runner = icarus.Runner(extra_files=files)
vcd = "test_%s.vcd" % self.__class__.__name__
self.sim = Simulator(self.tb, TopLevel(vcd), sim_runner=runner)
def test_reader():
print("*** Testing reader")
adrgen = SimActor(adrgen_gen(), ("address", Source, [("a", BV(30))]))
reader = dma_wishbone.Reader()
dumper = SimActor(dumper_gen(), ("data", Sink, [("d", BV(32))]))
g = DataFlowGraph()
g.add_connection(adrgen, reader)
g.add_connection(reader, dumper)
comp = CompositeActor(g)
peripheral = MyPeripheral()
interconnect = wishbone.InterconnectPointToPoint(reader.bus, peripheral.bus)
def end_simulation(s):
s.interrupt = adrgen.done and not s.rd(comp.busy)
fragment = (
comp.get_fragment() + peripheral.get_fragment() + interconnect.get_fragment() + Fragment(sim=[end_simulation])
)
sim = Simulator(fragment, Runner())
sim.run()
class TestConsumer(unittest.TestCase):
def setUp(self):
self.tb = TestBench()
self.sim = Simulator(self.tb)
def _run(self):
with self.sim:
self.sim.run(200)
def testConsumer2(self):
tests = [
{"start":0, "count": 4},
{"start":555, "count": 77}
]
def srcgen():
for t in tests:
yield Token('source', t)
yield
def sinkgen():
for test in tests:
for n, ck in enumerate(range(
test["start"], test["start"] + test["count"])):
last = n == test["count"] - 1
t = Token("sink", idle_wait=True)
yield t
self.assertEqual(t.value['d'], ck & 0xFF)
self.assertEqual(t.value['last'], last)
self.last = t.value
self.tb.setSeq(srcgen(), sinkgen())
self._run()
self.assertEqual(self.last, {"d":119, "last":1})
def test_writer():
print("*** Testing writer")
trgen = SimActor(trgen_gen(), ("address_data", Source, [("a", BV(30)), ("d", BV(32))]))
writer = dma_wishbone.Writer()
g = DataFlowGraph()
g.add_connection(trgen, writer)
comp = CompositeActor(g)
peripheral = MyPeripheral()
tap = wishbone.Tap(peripheral.bus)
interconnect = wishbone.InterconnectPointToPoint(writer.bus, peripheral.bus)
def end_simulation(s):
s.interrupt = trgen.done and not s.rd(comp.busy)
fragment = comp.get_fragment() \
+ peripheral.get_fragment() \
+ tap.get_fragment() \
+ interconnect.get_fragment() \
+ Fragment(sim=[end_simulation])
sim = Simulator(fragment, Runner())
sim.run()
def test_reader():
print("*** Testing reader")
adrgen = SimActor(adrgen_gen(), ("address", Source, [("a", BV(30))]))
reader = dma_wishbone.Reader()
dumper = SimActor(dumper_gen(), ("data", Sink, [("d", BV(32))]))
g = DataFlowGraph()
g.add_connection(adrgen, reader)
g.add_connection(reader, dumper)
comp = CompositeActor(g)
peripheral = MyPeripheral()
interconnect = wishbone.InterconnectPointToPoint(reader.bus, peripheral.bus)
def end_simulation(s):
s.interrupt = adrgen.done and not s.rd(comp.busy)
fragment = comp.get_fragment() \
+ peripheral.get_fragment() \
+ interconnect.get_fragment() \
+ Fragment(sim=[end_simulation])
sim = Simulator(fragment, Runner())
sim.run()
def main():
# Compute filter coefficients with SciPy.
coef = signal.remez(80, [0, 0.1, 0.1, 0.5], [1, 0])
fir = FIR(coef)
# Simulate for different frequencies and concatenate
# the results.
in_signals = []
out_signals = []
for frequency in [0.05, 0.07, 0.1, 0.15, 0.2]:
tb = TB(fir, frequency)
fragment = autofragment.from_local()
sim = Simulator(fragment, Runner())
sim.run(100)
in_signals += tb.inputs
out_signals += tb.outputs
# Plot data from the input and output waveforms.
plt.plot(in_signals)
plt.plot(out_signals)
plt.show()
# Print the Verilog source for the filter.
print(verilog.convert(fir.get_fragment(), ios={fir.i, fir.o}))
for i in packet(10, 0x20, 4):
yield i
for i in packet(10, 0x30, 2):
yield i
class SimSource(SimActor):
def __init__(self):
self.source = Endpoint(ULPI_DATA_D)
SimActor.__init__(self, gen())
self.submodules.w = Whacker(1024)
self.submodules.src = SimSource()
self.comb += self.src.source.connect(self.w.sink)
self.comb += self.src.busy.eq(0)
self.submodules.dmp = Dumper(D_LAST)
self.comb += self.w.source.connect(self.dmp.result)
self.comb += self.dmp.busy.eq(0)
if __name__ == '__main__':
from migen.sim.generic import Simulator, TopLevel
from migen.sim.icarus import Runner
tl = TopLevel("testwhacker.vcd")
tl.clock_domains[0].name_override = 'sys_clk'
test = TestWhacker()
sim = Simulator(test, tl, Runner(keep_files=True))
sim.run(2000)
# stop bit
selfp.pads.rx = 1
elif (i == 10):
selfp.pads.rx = 1
break
else:
selfp.pads.rx = 1 if (rx_value & 1) else 0
rx_value >>= 1
yield from self.wait_for(uart_period)
rx_value = ord(rx_string)
received_value = selfp.slave._r_rxtx.w
if (received_value == rx_value):
print("RX SUCCESS: ")
else:
print("RX FAILURE: ")
print("received " + chr(received_value))
while True:
yield
if __name__ == "__main__":
from migen.sim.generic import Simulator, TopLevel
from migen.sim import icarus
with Simulator(UARTTB(), TopLevel("top.vcd",
clk_period=int(1 / 0.08333333)),
icarus.Runner(keep_files=False)) as s:
s.run(20000)
def setUp(self):
self.tb = TB()
self.sim = Simulator(self.tb)
self.byte_list = [(1,0x40), (0,0xCA), (1,0x10), (0, 0xFE), (1, 0x41)]
def do_simulation(self, s):
if s.cycle_counter > 5 and s.cycle_counter %2 and self.byte_list:
b = self.byte_list[0]
print("WR %s" % repr(b))
self.byte_list = self.byte_list[1:]
s.wr(self.tr.sink.stb, 1)
s.wr(self.tr.sink.payload.d, b[1])
s.wr(self.tr.sink.payload.rxcmd, b[0])
else:
s.wr(self.tr.sink.stb,0)
if s.rd(self.tr.source.stb):
print("%02x %d" % (s.rd(self.tr.source.payload.d), s.rd(self.tr.source.payload.rxcmd)))
if __name__ == "__main__":
from migen.sim.generic import Simulator, TopLevel
tl = TopLevel("sdram.vcd")
test = TestFilt(tl.clock_domains[0])
sim = Simulator(test, tl)
sim.run(500)
selfp.dut.rtlink.o.stb = 1 # falling edge at fine_ts = 0
yield
selfp.dut.rtlink.o.stb = 0
yield
self.check_output(selfp, data=0)
yield
self.check_output(selfp, data=0)
selfp.dut.rtlink.o.data = 1
selfp.dut.rtlink.o.fine_ts = 7
selfp.dut.rtlink.o.stb = 1 # rising edge at fine_ts = 7
yield
selfp.dut.rtlink.o.stb = 0
yield
self.check_output(selfp, data=0b10000000)
if __name__ == "__main__":
import sys
from migen.sim.generic import Simulator, TopLevel
if len(sys.argv) != 2:
print("Incorrect command line")
sys.exit(1)
cls = {"output": _OutputTB, "inout": _InOutTB}[sys.argv[1]]
with Simulator(cls(), TopLevel("top.vcd", clk_period=int(1 / 0.125))) as s:
s.run()
def main():
tb = TB()
sim = Simulator(tb)
sim.run()
def main():
dut = Mem()
sim = Simulator(dut.get_fragment(), Runner())
# No need for a cycle limit here, we use sim.interrupt instead.
sim.run()
NET "{clk_ezusbfifo}" TNM_NET = "GRP_clk_ezusbfifo";
TIMESPEC "TS_cdc_fwd" =
FROM "GRP_clk_sys" TO "GRP_clk_ezusbfifo"
[delay] ns DATAPATHONLY;
TIMESPEC "TS_cdc_bwd" =
FROM "GRP_clk_ezusbfifo" TO "GRP_clk_sys"
[delay] ns DATAPATHONLY;
OFFSET = IN 15 ns VALID 30 ns BEFORE "{clk_if}";
OFFSET = OUT 15 ns AFTER "{clk_if}";
""".replace('[delay]',
str(0.5 * 33.33 * fraction[1] / fraction[0])),
clk_if=clk_if,
clk_sys=clk_sys,
clk_ezusbfifo=clk_ezusbfifo,
)
plat.build_cmdline(echo)
elif command == 'sim':
from migen.sim.generic import Simulator, TopLevel
echo = Echo(SimUSBActor(loop=True))
sim = Simulator(echo, TopLevel("echo.vcd"))
with sim:
sim.run()
else:
print('usage: python %s build|sim [options]' % sys.argv[0])
def setUp(self):
self.tb = TestBench()
self.sim = Simulator(self.tb)
def main():
dut = Counter()
# Instantiating the generic top-level ourselves lets us
# specify a VCD output file.
sim = Simulator(dut.get_fragment(), Runner(), TopLevel("my.vcd"))
sim.run(20)
def setUp(self):
self.tb = TestBench()
vcd = None
#vcd = "test_producer.vcd"
self.sim = Simulator(self.tb, TopLevel(vcd, vcd_level=3))
tRP=ns(15),
tRCD=ns(15),
tWR=ns(14),
tWTR=2,
tREFI=ns(64*1000*1000/4096, False),
tRFC=ns(66),
req_queue_size=8,
read_time=32,
write_time=16
)
sdram_pads = plat.request("sdram")
sdram_clk = plat.request("sdram_clock")
sdrphy = gensdrphy.GENSDRPHY(sdram_pads)
# This sets CL to 2 during LMR done on 1st cycle
sdram_pads.a.reset = 1<<5
s = MiniconTB(sdrphy, sdrphy.dfi, sdram_geom, sdram_timing, pads=sdram_pads, sdram_clk=sdram_clk)
extra_files = ["sdram_model/mt48lc4m16a2.v"]
if not isfile(extra_files[0]):
print("ERROR: You need to download Micron Verilog simulation model for MT48LC4M16A2 and put it in sdram_model/mt48lc4m16a2.v")
print("File can be downloaded from this URL: http://www.micron.com/-/media/documents/products/sim%20model/dram/dram/4054mt48lc4m16a2.zip")
sys.exit(1)
with Simulator(s, MyTopLevel("top.vcd", clk_period=int(1/0.08)), icarus.Runner(extra_files=extra_files, keep_files=True)) as sim:
sim.run(5000)
def setUp(self):
self.tb = TestBench()
vcd = None
vcd = "test_cmdproc.vcd"
self.sim = Simulator(self.tb, TopLevel(vcd, vcd_level=3))
