class TestPassCPU(unittest.TestCase):

    def setUp(self):
        self.cpu = PassCPU()
        self.sim = Simulator(self.cpu, TopLevel())

    def tearDown(self):
        self.sim.close()

    def testBasic(self):
        self.sim.wr(self.cpu.a, 1)
        self.sim.run(1)
        self.assertEqual(self.sim.rd(self.cpu.x), 1)
        self.sim.wr(self.cpu.a, 0)
        self.sim.run(1)
        self.assertEqual(self.sim.rd(self.cpu.x), 0)
class TestFourBitAdderCPU(unittest.TestCase):

    def setUp(self):
        self.cpu = FourBitAdderCPU()
        self.sim = Simulator(self.cpu, TopLevel())

    def tearDown(self):
        self.sim.close()

    def testBasic(self):
        self.sim.wr(self.cpu.op_a, 0)
        self.sim.wr(self.cpu.op_b, 0)
        self.sim.run(1)
        self.assertEqual(self.sim.rd(self.cpu.sum_out), 0)
        self.sim.wr(self.cpu.op_a, 1)
        self.sim.run(1)
        self.assertEqual(self.sim.rd(self.cpu.sum_out), 1)
        self.sim.wr(self.cpu.op_b, 1)
        self.sim.run(1)
        self.assertEqual(self.sim.rd(self.cpu.sum_out), 2)
        self.sim.wr(self.cpu.op_b, 2)
        self.sim.run(1)
        self.assertEqual(self.sim.rd(self.cpu.sum_out), 3)
        self.sim.wr(self.cpu.op_a, 12)
        self.sim.run(1)
        self.assertEqual(self.sim.rd(self.cpu.sum_out), 14)
        self.sim.wr(self.cpu.op_b, 5)
        self.sim.run(1)
        self.assertEqual(self.sim.rd(self.cpu.sum_out), 1)
class TestHalfAdderCPU(unittest.TestCase):

    def setUp(self):
        self.cpu = HalfAdderCPU()
        self.sim = Simulator(self.cpu, TopLevel())

    def tearDown(self):
        self.sim.close()

    def testBasic(self):
        self.sim.wr(self.cpu.op_a, 0)
        self.sim.wr(self.cpu.op_b, 0)
        self.sim.run(1)
        self.assertEqual(self.sim.rd(self.cpu.sum_out), 0)
        self.assertEqual(self.sim.rd(self.cpu.carry_out), 0)
        self.sim.wr(self.cpu.op_a, 1)
        self.sim.run(1)
        self.assertEqual(self.sim.rd(self.cpu.sum_out), 1)
        self.assertEqual(self.sim.rd(self.cpu.carry_out), 0)
        self.sim.wr(self.cpu.op_b, 1)
        self.sim.run(1)
        self.assertEqual(self.sim.rd(self.cpu.sum_out), 0)
        self.assertEqual(self.sim.rd(self.cpu.carry_out), 1)