def test_merge(self):
a = Bus(1)
b = Bus(1, 1)
buses = [a, b]
merged = Bus.merge(buses)
for a, b in zip(buses, merged):
self.assertEqual(a, b)
def test_get_op_len(self):
"""Test that op len enables bus methods to operate on both a length and
a Bus"""
b = Bus(1, 1)
b2 = Bus(4)
branched = b.branch(4)
self.assertEqual(len(branched), 4)
branched = b.branch(b2)
self.assertEqual(len(branched), 4)
def test_next(self):
bus_a = Bus(4)
bus_b = Bus(4)
gen = SignalGen(dict(a=bus_a, b=bus_b), self.signals)
self.assertEqual(int(bus_a.signal), 0)
self.assertEqual(int(bus_b.signal), 0)
gen.next()
self.assertEqual(int(bus_a.signal), 1)
self.assertEqual(int(bus_b.signal), 2)
gen.next()
self.assertEqual(int(bus_a.signal), 2)
self.assertEqual(int(bus_b.signal), 3)
gen.next()
self.assertEqual(int(bus_b.signal), 4)
def test_branch(self):
"""Test branching feature"""
a = Bus(1)
branched_a = a.branch(4)
self.assertEqual(len(branched_a), 4)
self.assertEqual(branched_a.signal, Signal(0, 4))
a.signal = 1
self.assertEqual(branched_a.signal, Signal(2**4 - 1, 4))
def test_sign_extend(self):
"""Test sign extension of Bus"""
b = Bus(2, 3)
seb = b.sign_extend(4)
self.assertEqual(len(seb), 4)
self.assertEqual(int(seb.signal), 15)
b.signal = 1
self.assertEqual(int(seb.signal), 1)
def test_setter(self):
a = Bus(2, 1)
with self.assertRaises(ValueError):
self.t.a = a
with self.assertRaises(ValueError):
self.t.en = a
with self.assertRaises(TypeError):
self.t.a = 5
def make(self):
i = self.get_inputs()
word_size = len(i.d)
mux = cb.SimpleMux(d1=i.d, s=i.l)
flip = sb.ResetFlipFlop(d=mux.y, clk=i.clk, reset=i.clr)
adder = cb.CPA(a=flip.q, b=Bus(word_size, 1))
mux.connect(d0=adder.s)
self.set_outputs(q=flip.q)
def test_init_bus(self):
a = Bus(4)
obj = self.obj(a=a)
for label in self.inputs:
self.assertTrue(label in obj.terminals)
for label in self.outputs:
self.assertTrue(label in obj.terminals)
terminal_lens = [term.size for term in obj.terminals.values()]
self.assertEqual([4] * 3, terminal_lens)
def test_slicing(self):
"""Test Bus slicing feature. Test index and ranges"""
b = Bus(4)
b.signal = 0b1010
bits = [0, 1, 0, 1]
for subbus, bit in zip(b, bits):
self.assertEqual(int(subbus.signal), bit)
b_slice = b[2:]
self.assertEqual(b_slice.signal, Signal(2, 2))
b_slice.signal = 0b11
self.assertEqual(b.signal, Signal(14, 4))
def make(self):
i = self.get_inputs()
self.set_outputs(wout=i.win)
self.set_tristate(win=i.lwin)
W = i.win
clk = i.clk
r = i.r
pc = sb.Counter(clk=clk, c=i.cp, q=W[:4],
r=r) #counter size 4, 4 LSB of W
pc_i = INV(a=i.ep)
pc.set_tristate(q=pc_i.y) #enable flag
self.pc = pc
acc = DoubleFlipFlop(d=W, qt=W, clk=clk, e=i.ea, l=i.la, r=r)
self.acc = acc
b_reg = sb.FlipFlop(d=W, clk=clk, l=i.lb, r=r) #no output tristate
self.br = b_reg
alu = ALU(a=acc.q, b=b_reg.q, sub=i.su, e=i.eu, s=W)
self.alu = alu
out_reg = sb.FlipFlop(d=W, clk=clk, l=i.lo,
r=r) #no output tristate as well
self.out_reg = out_reg
self.set_outputs(out=out_reg.q)
mar = sb.FlipFlop(d=W[:4], clk=clk, l=i.lm,
r=r) #mar has no otuput tristate either
self.mar = mar
rom = cb.ROM(8, addr=mar.q, q=W, ce=i.ce) #set en flag
self.rom = rom
ir = DoubleFlipFlop(d=W, qt=W, clk=clk, l=i.li, e=i.ei,
r=r) #set e l flags
self.ir = ir
self.set_outputs(iw=ir.q[4:])
mic = sb.Counter(clk=clk, size=3, bubbles=['clk'])
mic.c.set()
self.mic = mic
self.set_outputs(ic=mic.q)
eq_comp = cb.EqualityComparator(a=Bus(3, 5), b=mic.q)
reset_or = OR(a=r, b=eq_comp.eq)
mic.connect(r=reset_or.y)
def test_basic(self):
b = Bus(4)
self.assertEqual(len(b), 4)
self.assertEqual(b.signal, Signal(0, 4))
b.signal = 10
self.assertEqual(b.signal, Signal(10, 4))
def test_sweep(self):
#use truthtable obj to test this
bus_a = Bus()
bus_b = Bus()
d = dict(a=bus_a, b=bus_b)
gen = SignalGen.sweep(d)
def test_sweep_multibit(self):
#same as above
ba = Bus(2)
bb = Bus(2)
d = dict(a=ba, b=bb)
gen = SignalGen.sweep(d)
def test_add_single_bit(self):
"""Add two buses of len 1"""
a = Bus(1, 1)
b = Bus(1, 0)
c = a + b
self.assertEqual(c.signal.value, 2)
def test_propagate(self):
self.t.en = Bus(1, 0)
self.t.propagate()
self.assertEqual(self.t.y.signal, Signal(0, 1))
def test_vdd_extend(self):
b = Bus(2, 1) #0b01
seb = b.vdd_extend(4) #0b1101
self.assertEqual(len(seb), 4)
self.assertEqual(int(seb.signal), 13)
def setUp(self):
self.inputs = 'a b'.split()
self.outputs = ['y']
self.a = Bus(4, 10)
self.b = Bus(4, 7)
self.y = Bus(4, 11)
def test_zero_extend(self):
b = Bus(2, 3)
seb = b.zero_extend(4)
self.assertEqual(len(seb), 4)
self.assertEqual(int(seb.signal), 3)
def test_add_multi_bit(self):
"""Add two buses of len != 1"""
a = Bus(2, 1)
b = Bus(2, 2)
c = a + b
self.assertEqual(c.signal.value, 6)
def test_set_reset(self):
a = Bus(4)
a.set()
self.assertEqual(int(a.signal), 15)
a.reset()
self.assertEqual(int(a.signal), 0)
def setUp(self):
self.t = Terminal(1, 'test')
a = Bus(1, 1)
y = Bus(1, 0)
self.t.a = a
self.t.y = y
def test_split(self):
a = Bus(4, 0b0111)
buses = a.split()
for i, bus in enumerate(buses):
self.assertEqual(a[i].signal, bus.signal)