def make(self):
i = self.get_inputs()
instruction_encode_rom = cb.ROM(2, addr=i.d, ce=Bus.vdd())
instruction_encode_rom.fburn('instructions_encode.txt')
control_rom_bus = instruction_encode_rom.q + i.ic
control_rom = cb.ROM(12, addr=control_rom_bus, ce=Bus.vdd())
control_rom.fburn('control-rom.txt')
self.set_outputs(**{
label: bus
for label, bus in zip(self.output_labels, control_rom.q)
})
def test_memory(self):
"""Test ROM by assigning directly to the bit cells"""
words = 4
rom = cb.ROM(words, ce=Bus.vdd(), size=2)
signals = range(words)
rom.burn(signals)
for i in range(words):
rom.addr = i
self.assertEqual(int(rom.q.signal), i)
def make(self):
i = self.get_inputs()
word_size = len(i.q)
flip = FlipFlop(q=i.q, clk=i.clk)
c_gate = AND(a=Bus.vdd(), b=i.c)
adder = cb.CPA(a=flip.q, b=c_gate.y.zero_extend(flip.q))
reset_mux = cb.BaseMux(d0=adder.s, d1=Bus.gnd(adder.s), s=i.r)
flip.connect(d=reset_mux.y)
self.set_outputs(q=flip.q)
def make(self):
i = self.get_inputs()
W_bus = i.q
addr_decoder = Decoder(a=i.addr, e=Bus.vdd())
self.set_tristate(q=i.ce)
words = len(addr_decoder.y)
self.cells = [OR(size=self.word_size) for _ in range(words)]
for cell, bus in zip(self.cells, addr_decoder.y):
cell.set_tristate(y=bus)
cell.connect(y=W_bus)
def make(self):
i = self.get_inputs()
self.set_tristate(q=i.ce)
#cells have active low enable
addr_lines = cb.Decoder(a=i.addr, e=Bus.vdd())
cells = [
FlipFlop(clk=i.clk, d=i.d, e=en_bus, q=i.q, bubbles=['e'])
for en_bus in addr_lines.y
]
write_gates = [
AND(a=i.w, b=bus, bubbles=['y']) for bus in addr_lines.y
]
for gate, cell in zip(write_gates, cells):
cell.connect(l=gate.y)
def make(self):
i = self.get_inputs()
cpa = CPA(a=i.a, b=i.b, cin=Bus.vdd(), bubbles=['b'])
self.set_outputs(s=cpa.s)
