def main():
segmk = Segmaker("design.bits")
fuz_dir = os.getenv("FUZDIR", None)
assert fuz_dir
with open(os.path.join(fuz_dir, "attrs.json"), "r") as attr_file:
attrs = json.load(attr_file)
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
site = params['site']
for param, param_info in attrs.items():
value = params[param]
param_type = param_info["type"]
param_digits = param_info["digits"]
param_values = param_info["values"]
if param_type == BIN:
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=value, digits=param_digits)[::-1]
]
for i in range(param_digits):
segmk.add_site_tag(site, "%s[%u]" % (param, i), bitstr[i])
else:
assert param_type == BOOL
segmk.add_site_tag(site, param, value == "TRUE")
segmk.compile(bitfilter=bitfilter)
segmk.write()
def handle_design(prefix, second_pass):
segmk = Segmaker(prefix + ".bits")
tiledata = dict()
nlines = 0
print("Loading tags from design.txt.")
with open(prefix + ".txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
_, pip = pip.split(".")
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {"pips": set(), "srcs": set(), "dsts": set()}
if pip in pipdata:
assert pipdata[pip] == (src, dst)
else:
pipdata[pip] = (src, dst)
tiledata[tile]["pips"].add(pip)
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
if pnum == 1 or pdir == 0 or \
re.match(r"^(L[HV]B?)(_L)?(_B)?[0-9]", src) or \
re.match(r"^(L[HV]B?)(_L)?(_B)?[0-9]", dst) or \
re.match(r"^(CTRL|GFAN)(_L)?[0-9]", dst):
ignpip.add(pip)
nlines += 1
if nlines == 0:
return
for tile, pips_srcs_dsts in tiledata.items():
pips = pips_srcs_dsts["pips"]
srcs = pips_srcs_dsts["srcs"]
dsts = pips_srcs_dsts["dsts"]
for pip, src_dst in pipdata.items():
src, dst = src_dst
if pip in ignpip:
pass
elif pip in pips:
segmk.addtag(tile, "%s.%s" % (dst, src), 1)
elif src_dst[1] not in dsts:
segmk.addtag(tile, "%s.%s" % (dst, src), 0)
if second_pass:
segmk.compile()
segmk.write(prefix[7:])
def main():
segmk = Segmaker("design.bits")
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
site = params['site']
for param, _ in boolean_params:
value = params[param]
segmk.add_site_tag(site, param, value)
for param, digits in hex_params + int_params:
value = int(params[param])
bitstr = [
int(x)
for x in "{value:0{digits}b}".format(value=value,
digits=digits)[::-1]
]
for i in range(digits):
segmk.add_site_tag(site, '%s[%u]' % (param, i), bitstr[i])
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
tiledata = {}
pipdata = {}
ignpip = set()
tile_ports = {}
read_pip_data('gtp_common_mid_ck_mux.txt', pipdata, tile_ports)
print("Loading tags from design.txt.")
with open("design.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
if not tile.startswith('GTP_COMMON_MID'):
continue
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set()
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
if "HCLK_GTP_CK_MUX" not in src:
ignpip.add((src, dst))
for tile, pips_srcs_dsts in tiledata.items():
tile_type = pips_srcs_dsts["type"]
pips = pips_srcs_dsts["pips"]
for src, dst in pipdata["GTP_COMMON"]:
if (src, dst) in ignpip:
pass
elif (src, dst) in pips:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
elif src not in tiledata[tile]["srcs"] and dst not in tiledata[
tile]["dsts"]:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
tiledata = {}
pipdata = {}
ignpip = set()
tile_ports = {}
read_pip_data('pcie_int_interface_l.txt', pipdata, tile_ports)
read_pip_data('pcie_int_interface_r.txt', pipdata, tile_ports)
print("Loading tags from design.txt.")
with open("design.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
if not tile.startswith('PCIE_INT_INTERFACE'):
continue
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set()
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
for tile, pips_srcs_dsts in tiledata.items():
tile_type = pips_srcs_dsts["type"]
pips = pips_srcs_dsts["pips"]
for src, dst in pipdata[tile_type]:
if (src, dst) in ignpip:
pass
elif (src, dst) in pips:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
else:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def run():
segmk = Segmaker("design.bits")
clk_inverts = {}
with open('design.csv', 'r') as f:
for params in csv.DictReader(f):
clk_inverts[params['site']] = params
print("Loading tags")
f = open('params.jl', 'r')
f.readline()
for l in f:
j = json.loads(l)
ps = j['params']
assert j['module'] == 'my_RAMB18E1'
site = verilog.unquote(ps['LOC'])
bus_tags(segmk, ps, site)
if ps['RAM_MODE'] == '"TDP"':
rw_width_tags(segmk, ps, site)
segmk.add_site_tag(
site, 'SDP_READ_WIDTH_36', ps['RAM_MODE'] == '"SDP"'
and int(ps['READ_WIDTH_A']) == 36)
segmk.add_site_tag(
site, 'SDP_WRITE_WIDTH_36', ps['RAM_MODE'] == '"SDP"'
and int(ps['WRITE_WIDTH_B']) == 36)
if ps['READ_WIDTH_A'] < 36 and ps['WRITE_WIDTH_B'] < 36:
isinv_tags(segmk, ps, site, clk_inverts[site])
write_mode_tags(segmk, ps, site)
write_rstreg_priority(segmk, ps, site)
write_rdaddr_collision(segmk, ps, site)
def bitfilter(frame, bit):
# rw_width_tags() aliasing interconnect on large widths
return frame not in (0, 20, 21)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def run():
segmk = Segmaker("design.bits")
clk_inverts = {}
with open('design.csv', 'r') as f:
for params in csv.DictReader(f):
clk_inverts[params['site']] = params
print("Loading tags")
f = open('params.jl', 'r')
f.readline()
for l in f:
j = json.loads(l)
ps = j['params']
assert j['module'] == 'my_RAMB18E1'
site = verilog.unquote(ps['LOC'])
isinv_tags(segmk, ps, site, clk_inverts[site])
bus_tags(segmk, ps, site)
rw_width_tags(segmk, ps, site)
write_mode_tags(segmk, ps, site)
write_rstreg_priority(segmk, ps, site)
write_rdaddr_collision(segmk, ps, site)
def bitfilter(frame, bit):
# rw_width_tags() aliasing interconnect on large widths
return frame not in (20, 21)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
for tile_param in params:
for param, tag in (
('Y0_IN_USE', 'RAMB18_Y0.IN_USE'),
('Y1_IN_USE', 'RAMB18_Y1.IN_USE'),
('FIFO_Y0_IN_USE', 'RAMB18_Y0.FIFO_MODE'),
('FIFO_Y1_IN_USE', 'RAMB18_Y1.FIFO_MODE'),
):
segmk.add_tile_tag(tile_param['tile'], tag, tile_param[param])
segmk.compile(bitfilter=bitfilter)
segmk.write()
def run():
segmk = Segmaker("design.bits")
print("Loading tags")
f = open('params.jl', 'r')
f.readline()
for l in f:
j = json.loads(l)
bus_tags(segmk, j, j['site'])
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
for tile_param in params:
if tile_param['EN_SYN'] and tile_param['DATA_WIDTH'] == 4:
output_integer_tags(segmk,
tile_param,
'ALMOST_EMPTY_OFFSET',
invert=True)
output_integer_tags(segmk,
tile_param,
'ALMOST_FULL_OFFSET',
invert=True)
for param in ('EN_SYN', 'FIRST_WORD_FALL_THROUGH'):
segmk.add_tile_tag(tile_param['tile'], param, tile_param[param])
segmk.compile()
segmk.write()
def run():
segmk = Segmaker("design.bits")
print("Loading tags")
f = open('params.jl', 'r')
f.readline()
for l in f:
j = json.loads(l)
ps = j['params']
assert j['module'] == 'my_PLLE2_ADV'
site = verilog.unquote(ps['LOC'])
bus_tags(segmk, ps, site)
segmk.compile()
segmk.write()
def run():
segmk = Segmaker("design.bits")
print("Loading params")
f = open("params.json")
params = json.load(f)
params = {p["site"]: p for p in params}
print("Loading tags")
f = open('params.jl', 'r')
f.readline()
for l in f:
j = json.loads(l)
bus_tags(segmk, j, params, j['site'])
segmk.compile(bitfilter=bitfilter)
segmk.write()
#!/usr/bin/env python3
# FIXME: getting two bits
# 00_40 31_46
# Can we find instance where they are not aliased?
WA7USED = 0
import sys, re, os
from prjxray.segmaker import Segmaker
segmk = Segmaker("design.bits")
print("Loading tags")
'''
module,loc,c31,b31,a31
my_NDI1MUX_NI_NMC31,SLICE_X12Y100,1,1,0
my_NDI1MUX_NI_NMC31,SLICE_X12Y101,1,1,1
my_NDI1MUX_NI_NMC31,SLICE_X12Y102,1,1,1
'''
f = open('params.csv', 'r')
f.readline()
for l in f:
l = l.strip()
module, loc, c31, b31, a31 = l.split(',')
c31 = int(c31)
b31 = int(b31)
a31 = int(a31)
segmk.add_site_tag(loc, "ADI1MUX.AI", 1 ^ a31)
segmk.add_site_tag(loc, "BDI1MUX.BI", 1 ^ b31)
segmk.add_site_tag(loc, "CDI1MUX.CI", 1 ^ c31)
def main():
segmk = Segmaker("design.bits")
tiledata = {}
pipdata = {}
ignpip = set()
with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'clk_bufg', 'clk_bufg_bot_r.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
pipdata[tile_type].append((src, dst))
with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'clk_bufg', 'clk_bufg_top_r.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
pipdata[tile_type].append((src, dst))
print("Loading tags from design.txt.")
with open("design.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
if not tile.startswith('CLK_BUFG'):
continue
if tile.startswith('CLK_BUFG_REBUF'):
continue
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set()
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
muxed_src = re.match(
'^CLK_BUFG_(TOP|BOT)_R_CK_MUXED', src) is not None
if pnum == 1 or pdir == 0 or \
muxed_src:
ignpip.add((src, dst))
for tile, pips_srcs_dsts in tiledata.items():
tile_type = pips_srcs_dsts["type"]
pips = pips_srcs_dsts["pips"]
for src, dst in pipdata[tile_type]:
if (src, dst) in ignpip:
pass
elif (src, dst) in pips:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
elif dst not in tiledata[tile]["dsts"]:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
tiledata = {}
pipdata = {}
ignpip = set()
tile_ports = {}
with open(
os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'hclk_ioi3', 'hclk_ioi3.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
tile_ports[tile_type] = set()
pipdata[tile_type].append((src, dst))
tile_ports[tile_type].add(src)
tile_ports[tile_type].add(dst)
print("Loading tags from design.txt.")
with open("design.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
if not tile.startswith('HCLK_IOI3'):
continue
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set()
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
if "IDELAYCTRL" not in dst:
ignpip.add((src, dst))
for tile, pips_srcs_dsts in tiledata.items():
tile_type = pips_srcs_dsts["type"]
pips = pips_srcs_dsts["pips"]
for src, dst in pipdata[tile_type]:
if (src, dst) in ignpip:
pass
elif (src, dst) in pips:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
elif dst not in tiledata[tile]["dsts"]:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
tiledata = {}
pipdata = {}
ignpip = set()
tile_ports = {}
with open(
os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'hclk_cmt', 'hclk_cmt.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
tile_ports[tile_type] = set()
pipdata[tile_type].append((src, dst))
tile_ports[tile_type].add(src)
tile_ports[tile_type].add(dst)
with open(
os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'hclk_cmt', 'hclk_cmt_l.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
tile_ports[tile_type] = set()
pipdata[tile_type].append((src, dst))
tile_ports[tile_type].add(src)
tile_ports[tile_type].add(dst)
tile_to_cmt = {}
cmt_to_hclk_cmt = {}
with open(os.path.join(os.getenv('FUZDIR'), 'build',
'cmt_regions.csv')) as f:
for l in f:
site, cmt, tile = l.strip().split(',')
tile_to_cmt[tile] = cmt
if tile.startswith('HCLK_CMT'):
cmt_to_hclk_cmt[cmt] = tile
active_ioclks = set()
print("Loading tags from design.txt.")
with open("design.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if src in IOCLK_MAP:
active_ioclks.add(
(cmt_to_hclk_cmt[tile_to_cmt[tile]], IOCLK_MAP[src]))
if not tile.startswith('HCLK_CMT'):
continue
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set()
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
if pnum == 1 or pdir == 0:
ignpip.add((src, dst))
for tile, pips_srcs_dsts in tiledata.items():
tile_type = pips_srcs_dsts["type"]
pips = pips_srcs_dsts["pips"]
for src, dst in pipdata[tile_type]:
if (src, dst) in ignpip:
pass
elif (src, dst) in pips:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
elif dst not in tiledata[tile]["dsts"]:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
for port in tile_ports[tile_type]:
# These ones do not have any outgoing connections from the tile.
if "FREQ_REF" in port:
continue
# There seems to be no special bits related to use of
# HCLK_CMT_MUX_CLKINT_n wires.
if "HCLK_CMT_MUX_CLKINT" in port:
continue
# It seems that CCIOn_USED is not enabled when a net goes through
# FREQ_REFn. Do not emit this tag if this happens.
if "CCIO" in port:
n = int(port[-1])
dst = "HCLK_CMT_MUX_OUT_FREQ_REF{}".format(n)
if dst in tiledata[tile]["dsts"]:
continue
if port in tiledata[tile]["dsts"] or port in tiledata[tile]["srcs"]:
segmk.add_tile_tag(tile, "{}_USED".format(port), 1)
else:
segmk.add_tile_tag(tile, "{}_USED".format(port), 0)
for ioclk in IOCLK_SRCS:
if ioclk in tiledata[tile]["srcs"] or (tile,
ioclk) in active_ioclks:
segmk.add_tile_tag(tile, "{}_ACTIVE".format(ioclk), 1)
else:
segmk.add_tile_tag(tile, "{}_ACTIVE".format(ioclk), 0)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
designdata = {}
tiledata = {}
pipdata = {}
ppipdata = {}
ignpip = set()
all_clks = {}
piplists = ['cmt_top_l_lower_b.txt', 'cmt_top_r_lower_b.txt']
wirelists = ['cmt_top_l_lower_b_wires.txt', 'cmt_top_r_lower_b_wires.txt']
ppiplists = ['ppips_cmt_top_l_lower_b.db', 'ppips_cmt_top_r_lower_b.db']
# Load PIP lists
print("Loading PIP lists...")
for piplist in piplists:
with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'cmt_top_lower', piplist)) as f:
for l in f:
pip, is_directional = l.strip().split(' ')
tile_type, dst, src = pip.split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
all_clks[tile_type] = set()
pipdata[tile_type].append((src, dst))
if dst.split('_')[-1].startswith('CLK'):
all_clks[tile_type].add(src)
if not int(is_directional):
pipdata[tile_type].append((dst, src))
if src.split('_')[-1].startswith('CLK'):
all_clks[tile_type].add(dst)
wiredata = {}
for wirelist in wirelists:
with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'cmt_top_lower', wirelist)) as f:
for l in f:
tile_type, wire = l.strip().split()
if tile_type not in wiredata:
wiredata[tile_type] = set()
wiredata[tile_type].add(wire)
# Load PPIP lists (to exclude them)
print("Loading PPIP lists...")
for ppiplist in ppiplists:
fname = os.path.join(
os.getenv('FUZDIR'), '..', '071-ppips', 'build', ppiplist)
with open(fname, 'r') as f:
for l in f:
pip_data, pip_type = l.strip().split()
if pip_type != 'always':
continue
tile_type, dst, src = pip_data.split('.')
if tile_type not in ppipdata:
ppipdata[tile_type] = []
ppipdata[tile_type].append((src, dst))
# Load desgin data
print("Loading design data...")
with open("design.txt", "r") as f:
for line in f:
fields = line.strip().split(",")
designdata[fields[0]] = fields[1:]
with open("design_pips.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
if not tile.startswith('CMT_TOP'):
continue
if 'UPPER_B' in tile:
continue
if 'LOWER_T' in tile:
continue
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set(),
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
#if dst.startswith('CMT_TOP_R_LOWER_B_CLK') or \
# dst.startswith('CMT_TOP_L_LOWER_B_CLK'):
# ignpip.add((src, dst))
active_wires = {}
with open("design_wires.txt", "r") as f:
for l in f:
tile, wire = l.strip().split('/')
if tile not in active_wires:
active_wires[tile] = set()
active_wires[tile].add(wire)
tags = {}
# Populate IN_USE tags
for tile, (site, in_use) in designdata.items():
if tile not in tags:
tags[tile] = {}
tile_type = tile.rsplit("_", maxsplit=1)[0]
tags[tile]["IN_USE"] = int(in_use)
# Populate PIPs
active_clks = {}
for tile in tags.keys():
tile_type = tile.rsplit("_", maxsplit=1)[0]
in_use = tags[tile]["IN_USE"]
if not in_use:
active_pips = []
else:
active_pips = tiledata[tile]["pips"]
for src, dst in pipdata[tile_type]:
if (src, dst) in ignpip:
continue
if (src, dst) in ppipdata[tile_type]:
continue
tag = "{}.{}".format(merge_lr_wires(dst), merge_lr_wires(src))
val = in_use if (src, dst) in active_pips else False
if not (in_use and not val):
if tile not in active_clks:
active_clks[tile] = set()
active_clks[tile].add(src)
tags[tile][tag] = int(val)
for wire in wiredata[tile_type]:
if 'CLK' not in wire:
continue
if 'CLKOUT' in wire:
continue
if 'CLKFB' in wire:
continue
if 'REBUF' in wire:
continue
wire = merge_lr_wires(wire)
if tile not in active_wires:
active_wires[tile] = set()
segmk.add_tile_tag(
tile, '{}_ACTIVE'.format(wire), wire in active_wires[tile])
# Output tags
for tile, tile_tags in tags.items():
for t, v in tile_tags.items():
segmk.add_tile_tag(tile, t, v)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def run():
segmk = Segmaker("design.bits", verbose=True)
print("Loading tags")
with open('params.json', 'r') as fp:
data = json.load(fp)
used_dsps = set()
for params in data['instances']:
dsp = "DSP_0" if params['SITE'][-1] in "02468" else "DSP_1"
site = params['SITE']
if params['USE_DPORT'] == quote(
"TRUE") and params['USE_MULT'] != quote("NONE"):
add(segmk, site, dsp, 'ADREG', 0, to_int(params['ADREG']), 1)
add(segmk, site, dsp, 'ALUMODEREG', 0, to_int(params['ALUMODEREG']), 1)
if params['A_INPUT'] == quote("DIRECT"):
add(segmk, site, dsp, 'AREG_0', 0,
int(to_int(params['AREG']) == 0), 0, False)
add(segmk, site, dsp, 'AREG_2', 0,
int(to_int(params['AREG']) == 2), 0, False)
if params['B_INPUT'] == quote("DIRECT"):
add(segmk, site, dsp, 'BREG_0', 0,
int(to_int(params['BREG']) == 0), 0, False)
add(segmk, site, dsp, 'BREG_2', 0,
int(to_int(params['BREG']) == 2), 0, False)
if params['A_INPUT'] == quote("CASCADE"):
add(
segmk, site, dsp, 'AREG_2_ACASCREG_1', 0,
int(
to_int(params['AREG']) == 2
and to_int(params['ACASCREG']) == 1), 0, False)
add(
segmk, site, dsp, 'AREG_2_ACASCREG_1', 0,
int(
to_int(params['AREG']) == 2
and to_int(params['ACASCREG']) == 1), 1, False)
if params['B_INPUT'] == quote("CASCADE"):
add(
segmk, site, dsp, 'BREG_2_BCASCREG_1', 0,
int(
to_int(params['BREG']) == 2
and to_int(params['BCASCREG']) == 1), 0, False)
add(
segmk, site, dsp, 'BREG_2_BCASCREG_1', 0,
int(
to_int(params['BREG']) == 2
and to_int(params['BCASCREG']) == 1), 1, False)
add(segmk, site, dsp, 'CARRYINREG', 0, to_int(params['CARRYINREG']), 1)
add(segmk, site, dsp, 'CARRYINSELREG', 0,
to_int(params['CARRYINSELREG']), 1)
add(segmk, site, dsp, 'CREG', 0, to_int(params['CREG']), 1)
if params['USE_DPORT'] == quote(
"TRUE") and params['USE_MULT'] != quote("NONE"):
add(segmk, site, dsp, 'DREG', 0, to_int(params['DREG']), 1)
add(segmk, site, dsp, 'INMODEREG', 0, to_int(params['INMODEREG']), 1)
add(segmk, site, dsp, 'OPMODEREG', 0, to_int(params['OPMODEREG']), 1)
add(segmk, site, dsp, 'PREG', 0, to_int(params['PREG']), 1)
INPUT = {}
INPUT[quote('DIRECT')] = 0
INPUT[quote('CASCADE')] = 1
add(segmk, site, dsp, 'A_INPUT', 0, INPUT[params['A_INPUT']], 0)
add(segmk, site, dsp, 'B_INPUT', 0, INPUT[params['B_INPUT']], 0)
BOOL = {}
BOOL[quote('FALSE')] = 0
BOOL[quote('TRUE')] = 1
add(segmk, site, dsp, 'USE_DPORT', 0, BOOL[params['USE_DPORT']], 0)
add(segmk, site, dsp, 'USE_SIMD_FOUR12', 0,
params['USE_SIMD'] == quote("FOUR12"), 0, False)
add(segmk, site, dsp, 'USE_SIMD_FOUR12_TWO24', 0, params['USE_SIMD']
in (quote("TWO24"), quote("FOUR12")), 0, False)
MULT = {}
MULT[quote('NONE')] = 0
MULT[quote('MULTIPLY')] = 1
MULT[quote('DYNAMIC')] = 2
for i in range(2):
add(segmk, site, dsp, 'USE_MULT', i, MULT[params['USE_MULT']], 0)
add(segmk, site, dsp, 'MREG', 0, to_int(params['MREG']), 1)
AUTORESET = {}
AUTORESET[quote('NO_RESET')] = 0
AUTORESET[quote('RESET_NOT_MATCH')] = 1
AUTORESET[quote('RESET_MATCH')] = 2
add(segmk, site, dsp, 'AUTORESET_PATDET_RESET_NOT_MATCH', 0,
params['AUTORESET_PATDET'] == quote("RESET_NOT_MATCH"), 0, False)
add(
segmk, site, dsp, 'AUTORESET_PATDET_RESET', 0,
params['AUTORESET_PATDET']
in (quote("RESET_NOT_MATCH"), quote("RESET_MATCH")), 0, False)
for i in range(48):
add(segmk, site, dsp, 'MASK', i, to_int(params['MASK']), 0)
for i in range(48):
add(segmk, site, dsp, 'PATTERN', i, to_int(params['PATTERN']), 0)
if params['USE_PATTERN_DETECT'] == quote("PATDET"):
add_site_group_zero(segmk, site, dsp + ".", [
"SEL_MASK_%s" % x
for x in ["MASK", "C", "ROUNDING_MODE1", "ROUNDING_MODE2"]
], "SEL_MASK_MASK", "SEL_MASK_%s" % (params['SEL_MASK'][1:-1]))
USE_PATTERN_DETECT = {}
USE_PATTERN_DETECT[quote('NO_PATDET')] = 0
USE_PATTERN_DETECT[quote('PATDET')] = 1
add(segmk, site, dsp, 'USE_PATTERN_DETECT', 0,
USE_PATTERN_DETECT[params['USE_PATTERN_DETECT']], 0)
inv_ports = [
("ALUMODE", 4),
("CARRYIN", 1),
("CLK", 1),
("INMODE", 5),
("OPMODE", 7),
]
for port, width in inv_ports:
param = 'IS_{}_INVERTED'.format(port)
for i in range(width):
add(segmk, site, dsp, param, i, to_int(params[param]), 1,
width > 1)
segmk.compile()
segmk.write()
#!/usr/bin/env python3
import sys, os, re
from prjxray.segmaker import Segmaker
segmk = Segmaker("design_%s.bits" % sys.argv[1])
pipdata = dict()
ignpip = set()
print("Loading tags from design.txt.")
with open("design_%s.txt" % sys.argv[1], "r") as f:
for line in f:
tile, loc, mask, pattern = line.split()
dsp = "DSP_0" if loc[-1] in "02468" else "DSP_1"
mask = int(mask.replace("48'h", ""), 16)
pattern = int(pattern.replace("48'h", ""), 16)
for i in range(48):
segmk.add_tile_tag(tile, "%s.MASK[%d]" % (dsp, i), (mask >> i) & 1)
segmk.add_tile_tag(tile, "%s.PATTERN[%d]" % (dsp, i),
(pattern >> i) & 1)
segmk.compile()
segmk.write(suffix=sys.argv[1])
#!/usr/bin/env python3
import os
from prjxray.segmaker import Segmaker
segmk = Segmaker("design.bits")
tiledata = dict()
pipdata = set()
print("Loading tags from design.txt.")
with open("design.txt", "r") as f:
for line in f:
ab, dst, src = line.split()
tile, dst = dst.split("/")
_, src = src.split("/")
if tile not in tiledata:
tiledata[tile] = {
"pips": set(),
"nodes": set(),
}
if ab == "A":
tiledata[tile]["pips"].add((dst, src))
pipdata.add((dst, src))
else:
tiledata[tile]["nodes"].add(src)
tiledata[tile]["nodes"].add(dst)
#!/usr/bin/env python3
import sys, re
from prjxray.segmaker import Segmaker
segmk = Segmaker("design.bits")
tiledata = dict()
pipdata = dict()
ignpip = set()
print("Loading tags from design.txt.")
with open("design.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
_, pip = pip.split(".")
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {"pips": set(), "srcs": set(), "dsts": set()}
if pip in pipdata:
assert pipdata[pip] == (src, dst)
else:
pipdata[pip] = (src, dst)
tiledata[tile]["pips"].add(pip)
#!/usr/bin/env python3
from prjxray.segmaker import Segmaker
from prjxray import util
segmk = Segmaker("design.bits")
cache = dict()
print("Loading tags")
'''
module,loc,n
clb_NFFMUX_O5,SLICE_X12Y100,3
clb_NFFMUX_AX,SLICE_X13Y100,2
clb_NFFMUX_O6,SLICE_X14Y100,3
'''
f = open('params.csv', 'r')
f.readline()
for l in f:
module, loc, n = l.split(',')
n = int(n)
which = chr(ord('A') + n)
# clb_NFFMUX_AX => AX
src = module.replace('clb_NFFMUX_', '')
'''
AFFMUX
30_00 30_01 30_02 30_03
F78 1 1
CY 1 1
O5 1 1
AX 1
XOR 1
for arg in sys.argv[1:]:
with open(arg + ".txt", "r") as f:
for line in f:
tile, pip = line.split()
_, pip = pip.split("/")
tile_type, pip = pip.split(".")
src, dst = pip.split("->>")
tag = "%s.%s" % (dst, src)
tags[tag] = dst
if "HCLK_CK_BUFH" in src:
en_tag = "ENABLE_BUFFER.%s" % src
en_tags[en_tag] = src
for arg in sys.argv[1:]:
print("Processing %s." % arg)
segmk = Segmaker(arg + ".bits")
tiledata = dict()
pipdata = dict()
ignpip = set()
with open(arg + ".txt", "r") as f:
for line in f:
tile, pip = line.split()
_, pip = pip.split("/")
tile_type, pip = pip.split(".")
src, dst = pip.split("->>")
# FIXME: workaround for https://github.com/SymbiFlow/prjxray/issues/392
if "CLB_IO_CLK" not in segmk.grid[tile]["bits"]:
print("WARNING: dropping tile %s" % tile)
parser.add_argument('--todo',
action='store',
default='../../todo.txt',
help='todo file path')
parser.add_argument('--design',
action='store',
default='design.txt',
help='design description file path')
parser.add_argument('--verbose', action='store_true', help='')
parser.add_argument('--bits',
action='store',
default='design.bits',
help='bits file path')
args = parser.parse_args()
segmk = Segmaker(args.bits)
verbose = args.verbose
tiledata = dict()
pipdata = dict()
ignpip = set()
todo = set()
print("Loading todo from %s." % args.todo)
with open(args.todo, "r") as f:
for line in f:
line = tuple(line.strip().split("."))
verbose and print('todo', line)
todo.add(line)
def main():
segmk = Segmaker("design.bits")
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
for row in params:
base_name = 'BUFHCE_X{}Y{}'.format(row['x'], row['y'])
segmk.add_site_tag(row['site'], '{}.IN_USE'.format(base_name),
row['IN_USE'])
if not row['IN_USE']:
continue
segmk.add_site_tag(row['site'], '{}.INIT_OUT'.format(base_name),
row['INIT_OUT'])
segmk.add_site_tag(row['site'], '{}.ZINV_CE'.format(base_name),
1 ^ row['IS_CE_INVERTED'])
# SYNC is a zero pattern
for opt in ['ASYNC']:
segmk.add_site_tag(row['site'],
'{}.CE_TYPE.'.format(base_name) + opt,
verilog.unquote(row['CE_TYPE']) == opt)
segmk.compile()
segmk.write()
#!/usr/bin/env python3
from prjxray.segmaker import Segmaker
from prjxray import util
segmk = Segmaker("design.bits")
cache = dict()
print("Loading tags")
'''
module,loc,n
clb_NFFMUX_O5,SLICE_X12Y100,3
clb_NFFMUX_AX,SLICE_X13Y100,2
clb_NFFMUX_O6,SLICE_X14Y100,3
'''
f = open('params.csv', 'r')
f.readline()
for l in f:
module, loc, n = l.split(',')
n = int(n)
which = chr(ord('A') + n)
# clb_NFFMUX_AX => AX
src = module.replace('clb_NOUTMUX_', '')
'''
BOUTMUX
30_20 30_21 30_22 30_23
O6 1
O5 1 1
XOR 1
CY 1 1
F8 1 1
def main():
print("Loading tags")
segmk = Segmaker("design.bits")
'''
port,site,tile,pin,slew,drive,pulltype
di[0],IOB_X0Y107,LIOB33_X0Y107,A21,PULLDOWN
di[10],IOB_X0Y147,LIOB33_X0Y147,F14,PULLUP
'''
with open('params.jl', 'r') as f:
design = json.load(f)
for d in design:
site = d['site']
if skip_broken_tiles(d):
continue
iostandard = verilog.unquote(d['IOSTANDARD'])
stepdown = iostandard in STEPDOWN_IOSTANDARDS
segmk.add_site_tag(site, '_'.join(STEPDOWN_IOSTANDARDS), stepdown)
if d['type'] is None:
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
for drive in drives_for_iostandard(iostandard):
segmk.add_site_tag(
site,
'{}.DRIVE.I{}.IN_OUT_COMMON'.format(iostandard,
drive), 0)
elif d['type'] == 'IBUF':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
for drive in drives_for_iostandard(iostandard):
segmk.add_site_tag(
site,
'{}.DRIVE.I{}.IN_OUT_COMMON'.format(iostandard,
drive), 1)
elif d['type'] == 'OBUF':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
for drive in drives_for_iostandard(iostandard):
if drive == d['DRIVE']:
segmk.add_site_tag(
site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
iostandard, drive), 1)
else:
segmk.add_site_tag(
site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
iostandard, drive), 0)
elif d['type'] == 'IOBUF_INTERMDISABLE':
segmk.add_site_tag(site, 'INOUT', 1)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
if d['type'] is not None:
segmaker.add_site_group_zero(
segmk, site, "PULLTYPE.",
("NONE", "KEEPER", "PULLDOWN", "PULLUP"), "PULLDOWN",
verilog.unquote(d['PULLTYPE']))
if d['type'] == 'IBUF' or d['type'] is None:
continue
drive_opts = set()
for opt in ("LVCMOS25", "LVCMOS33", "LVCMOS18", "LVCMOS15",
"LVCMOS12", 'LVTTL'):
for drive_opt in ("4", "8", "12", "16", "24"):
if drive_opt == "16" and opt == "LVCMOS12":
continue
if drive_opt == "24" and opt not in ["LVCMOS18", 'LVTTL']:
continue
drive_opts.add(mk_drive_opt(opt, drive_opt))
segmaker.add_site_group_zero(segmk, site, '', drive_opts,
mk_drive_opt('LVCMOS25', '12'),
mk_drive_opt(iostandard, d['DRIVE']))
segmaker.add_site_group_zero(segmk, site, "SLEW.",
("SLOW", "FAST"), "FAST",
verilog.unquote(d['SLEW']))
if 'ibufdisable_wire' in d:
segmk.add_site_tag(site, 'IBUFDISABLE.I',
d['ibufdisable_wire'] != '0')
if 'intermdisable_wire' in d:
segmk.add_site_tag(site, 'INTERMDISABLE.I',
d['intermdisable_wire'] != '0')
segmk.compile(bitfilter=bitfilter)
segmk.write(allow_empty=True)
def run():
segmk = Segmaker("design.bits", verbose=True)
print("Loading tags")
with open('params.json', 'r') as fp:
data = json.load(fp)
for params in data['instances']:
dsp = "DSP_0" if params['SITE'][-1] in "02468" else "DSP_1"
site = params['SITE']
add(segmk, site, dsp, 'ADREG', 0, to_int(params['ADREG']), 0)
add(segmk, site, dsp, 'ALUMODEREG', 0, to_int(params['ALUMODEREG']), 1)
for i in range(2):
add(segmk, site, dsp, 'AREG', i, to_int(params['AREG']), 1)
for i in range(2):
add(segmk, site, dsp, 'ACASCREG', i, to_int(params['ACASCREG']), 1)
for i in range(2):
add(segmk, site, dsp, 'BREG', i, to_int(params['BREG']), 1)
for i in range(2):
add(segmk, site, dsp, 'BCASCREG', i, to_int(params['BCASCREG']), 1)
add(segmk, site, dsp, 'CARRYINREG', 0, to_int(params['CARRYINREG']), 1)
add(
segmk, site, dsp, 'CARRYINSELREG', 0,
to_int(params['CARRYINSELREG']), 1)
add(segmk, site, dsp, 'CREG', 0, to_int(params['CREG']), 1)
add(segmk, site, dsp, 'DREG', 0, to_int(params['DREG']), 0)
add(segmk, site, dsp, 'INMODEREG', 0, to_int(params['INMODEREG']), 1)
add(segmk, site, dsp, 'OPMODEREG', 0, to_int(params['OPMODEREG']), 1)
add(segmk, site, dsp, 'PREG', 0, to_int(params['PREG']), 1)
INPUT = {}
INPUT[quote('DIRECT')] = 0
INPUT[quote('CASCADE')] = 1
add(segmk, site, dsp, 'A_INPUT', 0, INPUT[params['A_INPUT']], 0)
add(segmk, site, dsp, 'B_INPUT', 0, INPUT[params['B_INPUT']], 0)
BOOL = {}
BOOL[quote('FALSE')] = 0
BOOL[quote('TRUE')] = 1
add(segmk, site, dsp, 'USE_DPORT', 0, BOOL[params['USE_DPORT']], 0)
SIMD = {}
SIMD[quote('ONE48')] = 0
SIMD[quote('TWO24')] = 1
SIMD[quote('FOUR12')] = 2
for i in range(2):
add(segmk, site, dsp, 'USE_SIMD', i, SIMD[params['USE_SIMD']], 0)
MULT = {}
MULT[quote('NONE')] = 0
MULT[quote('MULTIPLY')] = 1
MULT[quote('DYNAMIC')] = 2
for i in range(2):
add(segmk, site, dsp, 'USE_MULT', i, MULT[params['USE_MULT']], 0)
add(segmk, site, dsp, 'MREG', 0, to_int(params['MREG']), 1)
AUTORESET = {}
AUTORESET[quote('NO_RESET')] = 0
AUTORESET[quote('RESET_NOT_MATCH')] = 1
AUTORESET[quote('RESET_MATCH')] = 2
add(
segmk, site, dsp, 'AUTORESET_PATDET', 0,
AUTORESET[params['AUTORESET_PATDET']], 0)
add(
segmk, site, dsp, 'AUTORESET_PATDET', 1,
AUTORESET[params['AUTORESET_PATDET']], 1)
for i in range(48):
add(segmk, site, dsp, 'MASK', i, to_int(params['MASK']), 0)
for i in range(48):
add(segmk, site, dsp, 'PATTERN', i, to_int(params['PATTERN']), 0)
SEL_MASK = {}
SEL_MASK[quote('MASK')] = 0
SEL_MASK[quote('C')] = 1
SEL_MASK[quote('ROUNDING_MODE1')] = 2
SEL_MASK[quote('ROUNDING_MODE2')] = 3
for i in range(2):
add(
segmk, site, dsp, 'SEL_MASK', i, SEL_MASK[params['SEL_MASK']],
0)
USE_PATTERN_DETECT = {}
USE_PATTERN_DETECT[quote('NO_PATDET')] = 0
USE_PATTERN_DETECT[quote('PATDET')] = 1
add(
segmk, site, dsp, 'USE_PATTERN_DETECT', 0,
USE_PATTERN_DETECT[params['USE_PATTERN_DETECT']], 0)
segmk.compile()
segmk.write()
def main():
segmk = Segmaker("design.bits")
designdata = {}
tiledata = {}
pipdata = {}
ppipdata = {}
ignpip = set()
piplists = ['cmt_top_l_upper_t.txt', 'cmt_top_r_upper_t.txt']
ppiplists = ['ppips_cmt_top_l_upper_t.db', 'ppips_cmt_top_r_upper_t.db']
# Load PIP lists
print("Loading PIP lists...")
for piplist in piplists:
with open(
os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'cmt_top', piplist)) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
pipdata[tile_type].append((src, dst))
# Load PPIP lists (to exclude them)
print("Loading PPIP lists...")
for ppiplist in ppiplists:
fname = os.path.join(os.getenv('FUZDIR'), '..', '071-ppips', 'build',
ppiplist)
with open(fname, 'r') as f:
for l in f:
pip_data, pip_type = l.strip().split()
if pip_type != 'always':
continue
tile_type, dst, src = pip_data.split('.')
if tile_type not in ppipdata:
ppipdata[tile_type] = []
ppipdata[tile_type].append((src, dst))
# Load desgin data
print("Loading design data...")
with open("design.txt", "r") as f:
for line in f:
fields = line.strip().split(",")
designdata[fields[0]] = fields[1:]
with open("design_pips.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
if not tile.startswith('CMT_TOP'):
continue
if 'UPPER_B' in tile:
continue
if 'LOWER_T' in tile:
continue
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set(),
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
if dst.startswith('CMT_TOP_R_UPPER_T_CLK') or \
dst.startswith('CMT_TOP_L_UPPER_T_CLK'):
ignpip.add((src, dst))
tags = {}
# Populate IN_USE tags
for tile, (site, in_use) in designdata.items():
if tile not in tags:
tags[tile] = {}
tags[tile]["IN_USE"] = int(in_use)
# Populate PIPs
for tile in tags.keys():
tile_type = tile.rsplit("_", maxsplit=1)[0]
in_use = tags[tile]["IN_USE"]
internal_feedback = False
if not in_use:
active_pips = []
else:
active_pips = tiledata[tile]["pips"]
for src, dst in pipdata[tile_type]:
if (src, dst) in ignpip:
continue
if (src, dst) in ppipdata[tile_type]:
continue
tag = "{}.{}".format(dst, src)
val = in_use if (src, dst) in active_pips else False
if not (in_use and not val):
tags[tile][tag] = int(val)
# Output tags
for tile, tile_tags in tags.items():
for t, v in tile_tags.items():
segmk.add_tile_tag(tile, t, v)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
# Create map of iobank -> sites
iobanks = {}
site_to_iobank = {}
iobank_iostandards = {}
with open(os.path.join(os.getenv('FUZDIR'), 'build', 'iobanks.txt')) as f:
for l in f:
iob_site, iobank = l.strip().split(',')
iobank = int(iobank)
if iobank not in iobanks:
iobanks[iobank] = set()
iobanks[iobank].add(iob_site)
assert iob_site not in site_to_iobank
site_to_iobank[iob_site] = iobank
for iobank in iobanks:
iobank_iostandards[iobank] = set()
# Load a list of PUDC_B pin function tiles. They are configured differently
# by the vendor tools so need to be skipped
pudc_tiles = set()
with open(os.path.join(os.getenv('FUZDIR'), 'build',
'pudc_sites.csv')) as f:
for l in csv.DictReader(f):
pudc_tiles.add(l["tile"])
print("Loading tags")
segmk = Segmaker("design.bits")
'''
port,site,tile,pin,slew,drive,pulltype
di[0],IOB_X0Y107,LIOB33_X0Y107,A21,PULLDOWN
di[10],IOB_X0Y147,LIOB33_X0Y147,F14,PULLUP
'''
with open('params.json', 'r') as f:
design = json.load(f)
diff_pairs = set()
for d in design['tiles']:
iostandard = verilog.unquote(d['IOSTANDARD'])
if iostandard.startswith('DIFF_'):
diff_pairs.add(d['pair_site'])
for d in design['tiles']:
site = d['site']
if d['tile'] in pudc_tiles:
continue
if site in diff_pairs:
continue
iostandard = verilog.unquote(d['IOSTANDARD'])
if iostandard.startswith('DIFF_'):
iostandard = iostandard[5:]
iobank_iostandards[site_to_iobank[site]].add(iostandard)
segmk.add_site_tag(site,
'_'.join(STEPDOWN_IOSTANDARDS) + '.STEPDOWN',
iostandard in STEPDOWN_IOSTANDARDS)
if 'IN_TERM' in d:
segmaker.add_site_group_zero(segmk, site, 'IN_TERM.', [
'NONE', 'UNTUNED_SPLIT_40', 'UNTUNED_SPLIT_50',
'UNTUNED_SPLIT_60'
], 'NONE', d['IN_TERM'])
if d['type'] is None:
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.IN_ONLY'.format(iostandard), 0)
elif d['type'] == 'IBUF':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN_DIFF'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.IN_ONLY'.format(iostandard), 1)
segmk.add_tile_tag(d['tile'], 'IN_DIFF', 0)
if iostandard in IBUF_LOW_PWR_SUPPORTED:
segmk.add_site_tag(site, 'IBUF_LOW_PWR', d['IBUF_LOW_PWR'])
segmk.add_site_tag(site, 'ZIBUF_LOW_PWR',
1 ^ d['IBUF_LOW_PWR'])
elif d['type'] == 'IBUFDS':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN_DIFF'.format(iostandard), 1)
segmk.add_site_tag(d['pair_site'],
'{}.IN_DIFF'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.IN_ONLY'.format(iostandard), 1)
segmk.add_tile_tag(d['tile'], 'IN_DIFF', 1)
elif d['type'] == 'OBUF':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
segmk.add_tile_tag(d['tile'], 'OUT_DIFF', 0)
elif d['type'] == 'OBUFDS':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
segmk.add_tile_tag(d['tile'], 'OUT_DIFF', 1)
segmk.add_tile_tag(d['tile'], 'OUT_TDIFF', 0)
elif d['type'] == 'OBUFTDS':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
segmk.add_tile_tag(d['tile'], 'OUT_DIFF', 1)
segmk.add_tile_tag(d['tile'], 'OUT_TDIFF', 1)
elif d['type'] == 'IOBUF_INTERMDISABLE':
segmk.add_site_tag(site, 'INOUT', 1)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
if d['type'] is not None:
segmaker.add_site_group_zero(
segmk, site, "PULLTYPE.",
("NONE", "KEEPER", "PULLDOWN", "PULLUP"), "PULLDOWN",
verilog.unquote(d['PULLTYPE']))
if d['type'] in [None, 'IBUF', 'IBUFDS']:
continue
drive_opts = set()
for opt in ("LVCMOS25", "LVCMOS33", "LVCMOS18", "LVCMOS15",
"LVCMOS12", 'LVTTL'):
for drive_opt in ("4", "8", "12", "16", "24"):
if drive_opt == "16" and opt == "LVCMOS12":
continue
if drive_opt == "24" and opt not in ["LVCMOS18", 'LVTTL']:
continue
drive_opts.add(mk_drive_opt(opt, drive_opt))
drive_opts.add(mk_drive_opt("SSTL135", None))
segmaker.add_site_group_zero(segmk, site, '', drive_opts,
mk_drive_opt('LVCMOS25', '12'),
mk_drive_opt(iostandard, d['DRIVE']))
for opt in ["SLOW", "FAST"]:
segmk.add_site_tag(site, iostandard + ".SLEW." + opt,
opt == verilog.unquote(d['SLEW']))
if 'ibufdisable_wire' in d:
segmk.add_site_tag(site, 'IBUFDISABLE.I',
d['ibufdisable_wire'] != '0')
if 'intermdisable_wire' in d:
segmk.add_site_tag(site, 'INTERMDISABLE.I',
d['intermdisable_wire'] != '0')
site_to_cmt = {}
site_to_tile = {}
tile_to_cmt = {}
cmt_to_idelay = {}
with open(os.path.join(os.getenv('FUZDIR'), 'build',
'cmt_regions.csv')) as f:
for l in f:
site, tile, cmt = l.strip().split(',')
site_to_tile[site] = tile
site_to_cmt[site] = cmt
tile_to_cmt[tile] = cmt
# Given IDELAYCTRL's are only located in HCLK_IOI3 tiles, and
# there is only on HCLK_IOI3 tile per CMT, update
# CMT -> IDELAYCTRL / tile map.
if 'IDELAYCTRL' in site:
assert cmt not in cmt_to_idelay
cmt_to_idelay[cmt] = site, tile
# For each IOBANK with an active VREF set the feature
cmt_vref_active = set()
with open('iobank_vref.csv') as f:
for l in f:
iobank, vref = l.strip().split(',')
iobank = int(iobank)
cmt = None
for cmt_site in iobanks[iobank]:
if cmt_site in site_to_cmt:
cmt = site_to_cmt[cmt_site]
break
if cmt is None:
continue
cmt_vref_active.add(cmt)
_, hclk_cmt_tile = cmt_to_idelay[cmt]
opt = 'VREF.V_{:d}_MV'.format(int(float(vref) * 1000))
segmk.add_tile_tag(hclk_cmt_tile, opt, 1)
for iobank in iobank_iostandards:
if len(iobank_iostandards[iobank]) == 0:
continue
for cmt_site in iobanks[iobank]:
if cmt_site in site_to_cmt:
cmt = site_to_cmt[cmt_site]
break
if cmt is None:
continue
_, hclk_cmt_tile = cmt_to_idelay[cmt]
assert len(iobank_iostandards[iobank]) == 1, iobank_iostandards[iobank]
iostandard = list(iobank_iostandards[iobank])[0]
segmk.add_tile_tag(hclk_cmt_tile, 'STEPDOWN', iostandard
in STEPDOWN_IOSTANDARDS)
# For IOBANK's with no active VREF, clear all VREF options.
for cmt, (_, hclk_cmt_tile) in cmt_to_idelay.items():
if cmt in cmt_vref_active:
continue
for vref in (
.600,
.675,
.75,
.90,
):
opt = 'VREF.V_{:d}_MV'.format(int(vref * 1000))
segmk.add_tile_tag(hclk_cmt_tile, opt, 0)
segmk.compile(bitfilter=bitfilter)
segmk.write(allow_empty=True)
