def main():
segmk = Segmaker("design.bits")
tiledata = {}
pipdata = {}
ignpip = set()
tile_ports = {}
read_pip_data('gtp_common_mid_ck_mux.txt', pipdata, tile_ports)
print("Loading tags from design.txt.")
with open("design.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
if not tile.startswith('GTP_COMMON_MID'):
continue
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set()
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
if "HCLK_GTP_CK_MUX" not in src:
ignpip.add((src, dst))
for tile, pips_srcs_dsts in tiledata.items():
tile_type = pips_srcs_dsts["type"]
pips = pips_srcs_dsts["pips"]
for src, dst in pipdata["GTP_COMMON"]:
if (src, dst) in ignpip:
pass
elif (src, dst) in pips:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
elif src not in tiledata[tile]["srcs"] and dst not in tiledata[
tile]["dsts"]:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
tiledata = {}
pipdata = {}
ignpip = set()
tile_ports = {}
read_pip_data('pcie_int_interface_l.txt', pipdata, tile_ports)
read_pip_data('pcie_int_interface_r.txt', pipdata, tile_ports)
print("Loading tags from design.txt.")
with open("design.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
if not tile.startswith('PCIE_INT_INTERFACE'):
continue
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set()
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
for tile, pips_srcs_dsts in tiledata.items():
tile_type = pips_srcs_dsts["type"]
pips = pips_srcs_dsts["pips"]
for src, dst in pipdata[tile_type]:
if (src, dst) in ignpip:
pass
elif (src, dst) in pips:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
else:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
for row in params:
base_name = 'BUFR_Y{}'.format(row['y'])
segmk.add_tile_tag(
row['tile'], '{}.IN_USE'.format(base_name), row['IN_USE'])
if not row['IN_USE']:
continue
segmk.add_tile_tag(
row['tile'], '{}.BUFR_DIVIDE.BYPASS'.format(base_name),
'"BYPASS"' == row['BUFR_DIVIDE'])
for opt in range(1, 9):
if row['BUFR_DIVIDE'] == str(opt):
segmk.add_tile_tag(
row['tile'], '{}.BUFR_DIVIDE.D{}'.format(base_name, opt),
1)
elif '"BYPASS"' == row['BUFR_DIVIDE']:
segmk.add_tile_tag(
row['tile'], '{}.BUFR_DIVIDE.D{}'.format(base_name, opt),
0)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
db_root = get_db_root()
part = get_part()
clock_column = ClockColumn(db_root, part)
segmk = Segmaker("design.bits")
print("Loading tags from design.txt.")
with open("route.txt", "r") as f:
for line in f:
if 'CLK_BUFG_REBUF' not in line:
continue
parts = line.replace('{', '').replace('}', '').strip().replace(
'\t', ' ').split(' ')
dst = parts[0]
pip = parts[3]
tile_from_pip, pip = pip.split('/')
if 'CLK_BUFG_REBUF' not in tile_from_pip:
continue
tile_type, pip = pip.split('.')
assert tile_type == 'CLK_BUFG_REBUF'
wire_a, wire_b = pip.split('<<->>')
tile_from_wire, dst = dst.split('/')
assert dst == wire_a
if tile_from_wire == tile_from_pip:
b_to_a = wire_a == dst
a_to_b = not b_to_a
else:
b_to_a = wire_a != dst
a_to_b = not b_to_a
segmk.add_tile_tag(
tile_from_pip, '{}.{}'.format(wire_a, wire_b), b_to_a)
segmk.add_tile_tag(
tile_from_pip, '{}.{}'.format(wire_b, wire_a), a_to_b)
clock_column.enable_rebuf(tile_from_pip, wire_a)
for tile, gclk, active_below, active_above in clock_column.yield_rebuf_state(
):
segmk.add_tile_tag(
tile, 'GCLK{}_ENABLE_ABOVE'.format(gclk), active_above)
segmk.add_tile_tag(
tile, 'GCLK{}_ENABLE_BELOW'.format(gclk), active_below)
segmk.compile()
segmk.write(allow_empty=True)
def main():
segmk = Segmaker("design.bits")
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
for tile_param in params:
for param, tag in (
('Y0_IN_USE', 'RAMB18_Y0.IN_USE'),
('Y1_IN_USE', 'RAMB18_Y1.IN_USE'),
('FIFO_Y0_IN_USE', 'RAMB18_Y0.FIFO_MODE'),
('FIFO_Y1_IN_USE', 'RAMB18_Y1.FIFO_MODE'),
):
segmk.add_tile_tag(tile_param['tile'], tag, tile_param[param])
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
for tile_param in params:
if tile_param['EN_SYN'] and tile_param['DATA_WIDTH'] == 4:
output_integer_tags(segmk,
tile_param,
'ALMOST_EMPTY_OFFSET',
invert=True)
output_integer_tags(segmk,
tile_param,
'ALMOST_FULL_OFFSET',
invert=True)
for param in ('EN_SYN', 'FIRST_WORD_FALL_THROUGH'):
segmk.add_tile_tag(tile_param['tile'], param, tile_param[param])
segmk.compile()
segmk.write()
def main():
segmk = Segmaker("design.bits")
tiledata = {}
pipdata = {}
ignpip = set()
tile_ports = {}
with open(
os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'hclk_ioi3', 'hclk_ioi3.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
tile_ports[tile_type] = set()
pipdata[tile_type].append((src, dst))
tile_ports[tile_type].add(src)
tile_ports[tile_type].add(dst)
print("Loading tags from design.txt.")
with open("design.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
if not tile.startswith('HCLK_IOI3'):
continue
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set()
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
if "IDELAYCTRL" not in dst:
ignpip.add((src, dst))
for tile, pips_srcs_dsts in tiledata.items():
tile_type = pips_srcs_dsts["type"]
pips = pips_srcs_dsts["pips"]
for src, dst in pipdata[tile_type]:
if (src, dst) in ignpip:
pass
elif (src, dst) in pips:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
elif dst not in tiledata[tile]["dsts"]:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
tiledata = {}
pipdata = {}
ignpip = set()
with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'clk_bufg', 'clk_bufg_bot_r.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
pipdata[tile_type].append((src, dst))
with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'clk_bufg', 'clk_bufg_top_r.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
pipdata[tile_type].append((src, dst))
print("Loading tags from design.txt.")
with open("design.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
if not tile.startswith('CLK_BUFG'):
continue
if tile.startswith('CLK_BUFG_REBUF'):
continue
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set()
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
muxed_src = re.match(
'^CLK_BUFG_(TOP|BOT)_R_CK_MUXED', src) is not None
if pnum == 1 or pdir == 0 or \
muxed_src:
ignpip.add((src, dst))
for tile, pips_srcs_dsts in tiledata.items():
tile_type = pips_srcs_dsts["type"]
pips = pips_srcs_dsts["pips"]
for src, dst in pipdata[tile_type]:
if (src, dst) in ignpip:
pass
elif (src, dst) in pips:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
elif dst not in tiledata[tile]["dsts"]:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
segmk.compile(bitfilter=bitfilter)
segmk.write()
#!/usr/bin/env python3
import sys, os, re
from prjxray.segmaker import Segmaker
segmk = Segmaker("design_%s.bits" % sys.argv[1])
pipdata = dict()
ignpip = set()
print("Loading tags from design.txt.")
with open("design_%s.txt" % sys.argv[1], "r") as f:
for line in f:
tile, loc, mask, pattern = line.split()
dsp = "DSP_0" if loc[-1] in "02468" else "DSP_1"
mask = int(mask.replace("48'h", ""), 16)
pattern = int(pattern.replace("48'h", ""), 16)
for i in range(48):
segmk.add_tile_tag(tile, "%s.MASK[%d]" % (dsp, i), (mask >> i) & 1)
segmk.add_tile_tag(tile, "%s.PATTERN[%d]" % (dsp, i),
(pattern >> i) & 1)
segmk.compile()
segmk.write(suffix=sys.argv[1])
def main():
segmk = Segmaker("design.bits")
tiledata = {}
pipdata = {}
ignpip = set()
tile_ports = {}
with open(
os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'hclk_cmt', 'hclk_cmt.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
tile_ports[tile_type] = set()
pipdata[tile_type].append((src, dst))
tile_ports[tile_type].add(src)
tile_ports[tile_type].add(dst)
with open(
os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'hclk_cmt', 'hclk_cmt_l.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
tile_ports[tile_type] = set()
pipdata[tile_type].append((src, dst))
tile_ports[tile_type].add(src)
tile_ports[tile_type].add(dst)
tile_to_cmt = {}
cmt_to_hclk_cmt = {}
with open(os.path.join(os.getenv('FUZDIR'), 'build',
'cmt_regions.csv')) as f:
for l in f:
site, cmt, tile = l.strip().split(',')
tile_to_cmt[tile] = cmt
if tile.startswith('HCLK_CMT'):
cmt_to_hclk_cmt[cmt] = tile
active_ioclks = set()
print("Loading tags from design.txt.")
with open("design.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if src in IOCLK_MAP:
active_ioclks.add(
(cmt_to_hclk_cmt[tile_to_cmt[tile]], IOCLK_MAP[src]))
if not tile.startswith('HCLK_CMT'):
continue
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set()
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
if pnum == 1 or pdir == 0:
ignpip.add((src, dst))
for tile, pips_srcs_dsts in tiledata.items():
tile_type = pips_srcs_dsts["type"]
pips = pips_srcs_dsts["pips"]
for src, dst in pipdata[tile_type]:
if (src, dst) in ignpip:
pass
elif (src, dst) in pips:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
elif dst not in tiledata[tile]["dsts"]:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
for port in tile_ports[tile_type]:
# These ones do not have any outgoing connections from the tile.
if "FREQ_REF" in port:
continue
# There seems to be no special bits related to use of
# HCLK_CMT_MUX_CLKINT_n wires.
if "HCLK_CMT_MUX_CLKINT" in port:
continue
# It seems that CCIOn_USED is not enabled when a net goes through
# FREQ_REFn. Do not emit this tag if this happens.
if "CCIO" in port:
n = int(port[-1])
dst = "HCLK_CMT_MUX_OUT_FREQ_REF{}".format(n)
if dst in tiledata[tile]["dsts"]:
continue
if port in tiledata[tile]["dsts"] or port in tiledata[tile]["srcs"]:
segmk.add_tile_tag(tile, "{}_USED".format(port), 1)
else:
segmk.add_tile_tag(tile, "{}_USED".format(port), 0)
for ioclk in IOCLK_SRCS:
if ioclk in tiledata[tile]["srcs"] or (tile,
ioclk) in active_ioclks:
segmk.add_tile_tag(tile, "{}_ACTIVE".format(ioclk), 1)
else:
segmk.add_tile_tag(tile, "{}_ACTIVE".format(ioclk), 0)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
tiledata = {}
pipdata = {}
ignpip = set()
tile_ports = {}
with open(
os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'hclk_cmt', 'hclk_cmt.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
tile_ports[tile_type] = set()
pipdata[tile_type].append((src, dst))
tile_ports[tile_type].add(src)
tile_ports[tile_type].add(dst)
with open(
os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'hclk_cmt', 'hclk_cmt_l.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
tile_ports[tile_type] = set()
pipdata[tile_type].append((src, dst))
tile_ports[tile_type].add(src)
tile_ports[tile_type].add(dst)
tile_to_cmt = {}
cmt_to_hclk_cmt = {}
with open(os.path.join(os.getenv('FUZDIR'), 'build',
'cmt_regions.csv')) as f:
for l in f:
site, cmt, tile = l.strip().split(',')
tile_to_cmt[tile] = cmt
if tile.startswith('HCLK_CMT'):
cmt_to_hclk_cmt[cmt] = tile
active_ioclks = set()
print("Loading tags from design.txt.")
with open("design.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if src in IOCLK_MAP:
active_ioclks.add(
(cmt_to_hclk_cmt[tile_to_cmt[tile]], IOCLK_MAP[src]))
if not tile.startswith('HCLK_CMT'):
continue
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set()
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
if pnum == 1 or pdir == 0:
ignpip.add((src, dst))
for tile, pips_srcs_dsts in tiledata.items():
tile_type = pips_srcs_dsts["type"]
pips = pips_srcs_dsts["pips"]
for src, dst in pipdata[tile_type]:
if (src, dst) in ignpip:
pass
elif (src, dst) in pips:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
elif dst not in tiledata[tile]["dsts"]:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
for port in tile_ports[tile_type]:
if port in tiledata[tile]["dsts"] or port in tiledata[tile]["srcs"]:
segmk.add_tile_tag(tile, "{}_USED".format(port), 1)
else:
segmk.add_tile_tag(tile, "{}_USED".format(port), 0)
for ioclk in IOCLK_SRCS:
if ioclk in tiledata[tile]["srcs"] or (tile,
ioclk) in active_ioclks:
segmk.add_tile_tag(tile, "{}_ACTIVE".format(ioclk), 1)
else:
segmk.add_tile_tag(tile, "{}_ACTIVE".format(ioclk), 0)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
# Create map of iobank -> sites
iobanks = {}
site_to_iobank = {}
iobank_iostandards = {}
with open(os.path.join(os.getenv('FUZDIR'), 'build', 'iobanks.txt')) as f:
for l in f:
iob_site, iobank = l.strip().split(',')
iobank = int(iobank)
if iobank not in iobanks:
iobanks[iobank] = set()
iobanks[iobank].add(iob_site)
assert iob_site not in site_to_iobank
site_to_iobank[iob_site] = iobank
for iobank in iobanks:
iobank_iostandards[iobank] = set()
# Load a list of PUDC_B pin function tiles. They are configured differently
# by the vendor tools so need to be skipped
pudc_tiles = set()
with open(os.path.join(os.getenv('FUZDIR'), 'build',
'pudc_sites.csv')) as f:
for l in csv.DictReader(f):
pudc_tiles.add(l["tile"])
print("Loading tags")
segmk = Segmaker("design.bits")
'''
port,site,tile,pin,slew,drive,pulltype
di[0],IOB_X0Y107,LIOB33_X0Y107,A21,PULLDOWN
di[10],IOB_X0Y147,LIOB33_X0Y147,F14,PULLUP
'''
with open('params.json', 'r') as f:
design = json.load(f)
diff_pairs = set()
for d in design['tiles']:
iostandard = verilog.unquote(d['IOSTANDARD'])
if iostandard.startswith('DIFF_'):
diff_pairs.add(d['pair_site'])
for d in design['tiles']:
site = d['site']
if d['tile'] in pudc_tiles:
continue
if site in diff_pairs:
continue
iostandard = verilog.unquote(d['IOSTANDARD'])
if iostandard.startswith('DIFF_'):
iostandard = iostandard[5:]
iobank_iostandards[site_to_iobank[site]].add(iostandard)
segmk.add_site_tag(site,
'_'.join(STEPDOWN_IOSTANDARDS) + '.STEPDOWN',
iostandard in STEPDOWN_IOSTANDARDS)
if 'IN_TERM' in d:
segmaker.add_site_group_zero(segmk, site, 'IN_TERM.', [
'NONE', 'UNTUNED_SPLIT_40', 'UNTUNED_SPLIT_50',
'UNTUNED_SPLIT_60'
], 'NONE', d['IN_TERM'])
if d['type'] is None:
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.IN_ONLY'.format(iostandard), 0)
elif d['type'] == 'IBUF':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN_DIFF'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.IN_ONLY'.format(iostandard), 1)
segmk.add_tile_tag(d['tile'], 'IN_DIFF', 0)
if iostandard in IBUF_LOW_PWR_SUPPORTED:
segmk.add_site_tag(site, 'IBUF_LOW_PWR', d['IBUF_LOW_PWR'])
segmk.add_site_tag(site, 'ZIBUF_LOW_PWR',
1 ^ d['IBUF_LOW_PWR'])
elif d['type'] == 'IBUFDS':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN_DIFF'.format(iostandard), 1)
segmk.add_site_tag(d['pair_site'],
'{}.IN_DIFF'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.IN_ONLY'.format(iostandard), 1)
segmk.add_tile_tag(d['tile'], 'IN_DIFF', 1)
elif d['type'] == 'OBUF':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
segmk.add_tile_tag(d['tile'], 'OUT_DIFF', 0)
elif d['type'] == 'OBUFDS':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
segmk.add_tile_tag(d['tile'], 'OUT_DIFF', 1)
segmk.add_tile_tag(d['tile'], 'OUT_TDIFF', 0)
elif d['type'] == 'OBUFTDS':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
segmk.add_tile_tag(d['tile'], 'OUT_DIFF', 1)
segmk.add_tile_tag(d['tile'], 'OUT_TDIFF', 1)
elif d['type'] == 'IOBUF_INTERMDISABLE':
segmk.add_site_tag(site, 'INOUT', 1)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
if d['type'] is not None:
segmaker.add_site_group_zero(
segmk, site, "PULLTYPE.",
("NONE", "KEEPER", "PULLDOWN", "PULLUP"), "PULLDOWN",
verilog.unquote(d['PULLTYPE']))
if d['type'] in [None, 'IBUF', 'IBUFDS']:
continue
drive_opts = set()
for opt in ("LVCMOS25", "LVCMOS33", "LVCMOS18", "LVCMOS15",
"LVCMOS12", 'LVTTL'):
for drive_opt in ("4", "8", "12", "16", "24"):
if drive_opt == "16" and opt == "LVCMOS12":
continue
if drive_opt == "24" and opt not in ["LVCMOS18", 'LVTTL']:
continue
drive_opts.add(mk_drive_opt(opt, drive_opt))
drive_opts.add(mk_drive_opt("SSTL135", None))
segmaker.add_site_group_zero(segmk, site, '', drive_opts,
mk_drive_opt('LVCMOS25', '12'),
mk_drive_opt(iostandard, d['DRIVE']))
for opt in ["SLOW", "FAST"]:
segmk.add_site_tag(site, iostandard + ".SLEW." + opt,
opt == verilog.unquote(d['SLEW']))
if 'ibufdisable_wire' in d:
segmk.add_site_tag(site, 'IBUFDISABLE.I',
d['ibufdisable_wire'] != '0')
if 'intermdisable_wire' in d:
segmk.add_site_tag(site, 'INTERMDISABLE.I',
d['intermdisable_wire'] != '0')
site_to_cmt = {}
site_to_tile = {}
tile_to_cmt = {}
cmt_to_idelay = {}
with open(os.path.join(os.getenv('FUZDIR'), 'build',
'cmt_regions.csv')) as f:
for l in f:
site, tile, cmt = l.strip().split(',')
site_to_tile[site] = tile
site_to_cmt[site] = cmt
tile_to_cmt[tile] = cmt
# Given IDELAYCTRL's are only located in HCLK_IOI3 tiles, and
# there is only on HCLK_IOI3 tile per CMT, update
# CMT -> IDELAYCTRL / tile map.
if 'IDELAYCTRL' in site:
assert cmt not in cmt_to_idelay
cmt_to_idelay[cmt] = site, tile
# For each IOBANK with an active VREF set the feature
cmt_vref_active = set()
with open('iobank_vref.csv') as f:
for l in f:
iobank, vref = l.strip().split(',')
iobank = int(iobank)
cmt = None
for cmt_site in iobanks[iobank]:
if cmt_site in site_to_cmt:
cmt = site_to_cmt[cmt_site]
break
if cmt is None:
continue
cmt_vref_active.add(cmt)
_, hclk_cmt_tile = cmt_to_idelay[cmt]
opt = 'VREF.V_{:d}_MV'.format(int(float(vref) * 1000))
segmk.add_tile_tag(hclk_cmt_tile, opt, 1)
for iobank in iobank_iostandards:
if len(iobank_iostandards[iobank]) == 0:
continue
for cmt_site in iobanks[iobank]:
if cmt_site in site_to_cmt:
cmt = site_to_cmt[cmt_site]
break
if cmt is None:
continue
_, hclk_cmt_tile = cmt_to_idelay[cmt]
assert len(iobank_iostandards[iobank]) == 1, iobank_iostandards[iobank]
iostandard = list(iobank_iostandards[iobank])[0]
segmk.add_tile_tag(hclk_cmt_tile, 'STEPDOWN', iostandard
in STEPDOWN_IOSTANDARDS)
# For IOBANK's with no active VREF, clear all VREF options.
for cmt, (_, hclk_cmt_tile) in cmt_to_idelay.items():
if cmt in cmt_vref_active:
continue
for vref in (
.600,
.675,
.75,
.90,
):
opt = 'VREF.V_{:d}_MV'.format(int(vref * 1000))
segmk.add_tile_tag(hclk_cmt_tile, opt, 0)
segmk.compile(bitfilter=bitfilter)
segmk.write(allow_empty=True)
def main():
segmk = Segmaker("design.bits")
fuz_dir = os.getenv("FUZDIR", None)
assert fuz_dir
with open(os.path.join(fuz_dir, "attrs.json"), "r") as attr_file:
attrs = json.load(attr_file)
print("Loading tags")
with open("params.json") as f:
params_dict = json.load(f)
tile_type = params_dict["tile_type"]
params_list = params_dict["params"]
for params in params_list:
site = params["site"]
tile = params["tile"]
if "GTPE2_COMMON" not in site:
continue
in_use = params["IN_USE"]
segmk.add_site_tag(site, "IN_USE", in_use)
if in_use:
for param, param_info in attrs.items():
value = params[param]
param_type = param_info["type"]
param_digits = param_info["digits"]
param_values = param_info["values"]
if param_type == INT:
param_encodings = param_info["encoding"]
param_encoding = param_encodings[param_values.index(value)]
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=param_encoding, digits=param_digits)[::-1]
]
for i in range(param_digits):
segmk.add_site_tag(site, '%s[%u]' % (param, i),
bitstr[i])
else:
assert param_type == BIN
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=value, digits=param_digits)[::-1]
]
for i in range(param_digits):
segmk.add_site_tag(site, "%s[%u]" % (param, i),
bitstr[i])
for param in ["PLL0LOCKDETCLK", "PLL1LOCKDETCLK", "DRPCLK"]:
segmk.add_site_tag(site, "ZINV_" + param, 1 ^ params[param])
for param in [
"GTREFCLK0_USED", "GTREFCLK1_USED", "BOTH_GTREFCLK_USED"
]:
segmk.add_site_tag(site, param, params[param])
segmk.add_tile_tag(tile, "ENABLE_DRP", params["ENABLE_DRP"])
for params in params_list:
site = params["site"]
if "IBUFDS_GTE2" not in site:
continue
in_use = params["IN_USE"]
segmk.add_site_tag(site, "IN_USE", in_use)
if in_use:
tile = params["tile"]
for param in ["CLKRCV_TRST", "CLKCM_CFG"]:
value = params[param]
segmk.add_site_tag(site, param, "TRUE" in value)
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=params["CLKSWING_CFG"], digits=2)[::-1]
]
for i in range(2):
segmk.add_tile_tag(tile, "IBUFDS_GTE2.%s[%u]" % (param, i),
bitstr[i])
if tile_type.startswith("GTP_COMMON_MID"):
bitfilter = bitfilter_gtp_common_mid
elif tile_type == "GTP_COMMON":
bitfilter = bitfilter_gtp_common
else:
assert False, tile_type
segmk.compile(bitfilter=bitfilter)
segmk.write()
en_tags[en_tag] = src
for arg in sys.argv[1:]:
print("Processing %s." % arg)
segmk = Segmaker(arg + ".bits")
tiledata = dict()
pipdata = dict()
ignpip = set()
with open(arg + ".txt", "r") as f:
for line in f:
tile, pip = line.split()
_, pip = pip.split("/")
tile_type, pip = pip.split(".")
src, dst = pip.split("->>")
tag = "%s.%s" % (dst, src)
segmk.add_tile_tag(tile, tag, 1)
if "HCLK_CK_BUFH" in src:
en_tag = "ENABLE_BUFFER.%s" % src
segmk.add_tile_tag(tile, en_tag, 1)
for tag, tag_dst in tags.items():
if tag_dst != dst:
segmk.add_tile_tag(tile, tag, 0)
for en_tag, en_tag_src in en_tags.items():
if en_tag_src != src:
segmk.add_tile_tag(tile, en_tag, 0)
segmk.compile()
segmk.write(arg)
tiledata[tile]["pips"].add(pip)
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
imux = re.match('^IMUX(_L)?[0-9]+$', dst) is not None
if not imux:
ignpip.add(pip)
for tile, pips_srcs_dsts in tiledata.items():
pips = pips_srcs_dsts["pips"]
srcs = pips_srcs_dsts["srcs"]
dsts = pips_srcs_dsts["dsts"]
for pip, src_dst in pipdata.items():
src, dst = src_dst
if pip in ignpip:
pass
else:
if re.match('^GFAN[01]', src):
print(tile, src, dst, pip in pips)
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), pip in pips)
segmk.compile(bitfilter=get_bitfilter(os.getenv('XRAY_DATABASE'), 'INT'))
segmk.write()
def main():
segmk = Segmaker("design.bits")
tiledata = {}
pipdata = {}
clk_list = {}
casco_list = {}
ignpip = set()
with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'clk_hrow', 'clk_hrow_bot_r.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
clk_list[tile_type] = set()
casco_list[tile_type] = set()
pipdata[tile_type].append((src, dst))
if 'CASCO' in dst:
casco_list[tile_type].add(dst)
if dst.startswith('CLK_HROW_CK_MUX_OUT_'):
clk_list[tile_type].add(src)
if dst.startswith('CLK_HROW_BOT_R_CK_BUFG_'):
if 'CASCIN' not in src:
clk_list[tile_type].add(src)
with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'clk_hrow', 'clk_hrow_top_r.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
clk_list[tile_type] = set()
casco_list[tile_type] = set()
pipdata[tile_type].append((src, dst))
if 'CASCO' in dst:
casco_list[tile_type].add(dst)
if dst.startswith('CLK_HROW_CK_MUX_OUT_'):
clk_list[tile_type].add(src)
if dst.startswith('CLK_HROW_TOP_R_CK_BUFG_'):
if 'CASCIN' not in src:
clk_list[tile_type].add(src)
print("Loading tags from design.txt.")
with open("design.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
if not tile.startswith('CLK_HROW'):
continue
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set()
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
if pnum == 1 or pdir == 0:
ignpip.add((src, dst))
active_gclks = {}
active_clks = {}
for tile, pips_srcs_dsts in tiledata.items():
tile_type = pips_srcs_dsts["type"]
pips = pips_srcs_dsts["pips"]
if tile not in active_clks:
active_clks[tile] = set()
for src, dst in pips_srcs_dsts["pips"]:
active_clks[tile].add(src)
if 'GCLK' in src:
if src not in active_gclks:
active_gclks[src] = set()
active_gclks[src].add(tile)
for src, dst in pipdata[tile_type]:
if (src, dst) in ignpip:
pass
elif (src, dst) in pips:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
elif dst not in tiledata[tile]["dsts"]:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
for tile_type, srcs in clk_list.items():
for tile, pips_srcs_dsts in tiledata.items():
for src in srcs:
#Don't solve fake features
if not src_has_active_bit(src):
continue
if 'GCLK' not in src:
active = src in active_clks[tile]
segmk.add_tile_tag(tile, '{}_ACTIVE'.format(src), active)
else:
if src not in active_gclks:
segmk.add_tile_tag(tile, '{}_ACTIVE'.format(src), 0)
elif tile in active_gclks[src]:
segmk.add_tile_tag(tile, '{}_ACTIVE'.format(src), 1)
segmk.compile()
segmk.write()
src, dst = src_dst
# BRAM_R has some _R_ added to some pips. Because BRAM_L and BRAM_R
# appears to shares all bits, overlap the names during fuzzing to avoid
# extra work.
#
# BRAM.BRAM_ADDRARDADDRL0.BRAM_IMUX_R_ADDRARDADDRL0
#
# becomes
#
# BRAM.BRAM_ADDRARDADDRL0.BRAM_IMUX_ADDRARDADDRL0
src_no_r = src.replace('BRAM_R_IMUX_ADDR', 'BRAM_IMUX_ADDR')
if pip in ignpip:
pass
elif pip in pips:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src_no_r), 1)
elif src_dst[1] not in dsts:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src_no_r), 0)
m = CASCOUT_RE.match(dst)
if m and pip in pips:
active_cascout.add(m.group(1))
for group in ['BWR', 'ARD']:
segmk.add_tile_tag(tile, 'CASCOUT_{}_ACTIVE'.format(group), group
in active_cascout)
segmk.compile()
segmk.write()
def main():
segmk = Segmaker("design.bits")
tiledata = {}
pipdata = {}
ignpip = set()
with open(
os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build', 'ioi3',
'lioi3.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
pipdata[tile_type].append((src, dst))
with open(
os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build', 'ioi3',
'rioi3.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
pipdata[tile_type].append((src, dst))
print("Loading tags from design.txt.")
with open("design.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
if not tile.startswith('LIOI3') and not tile.startswith('RIOI3'):
continue
log = open("log.txt", "a")
print(line, file=log)
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set(),
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
for tile, pips_srcs_dsts in tiledata.items():
tile_type = pips_srcs_dsts["type"]
if tile_type.startswith('LIOI3'):
tile_type = 'LIOI3'
elif tile_type.startswith('RIOI3'):
tile_type = 'RIOI3'
for src, dst in pipdata[tile_type]:
if (src, dst) in ignpip:
pass
if re.match(r'.*PHASER.*', src) or re.match(
r'.*CLKDIV[PFB].*', dst):
pass
elif (src, dst) in tiledata[tile]["pips"]:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
elif dst not in tiledata[tile]["dsts"]:
disable_pip = True
if dst == 'IOI_OCLKM_0' and 'IOI_OCLK_0' in tiledata[tile][
"dsts"]:
disable_pip = False
if dst == 'IOI_OCLKM_1' and 'IOI_OCLK_1' in tiledata[tile][
"dsts"]:
disable_pip = False
if disable_pip:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
table = clk_table.get_clk_table()
print("Loading tags from design.txt.")
active_gclks = {}
active_clks = {}
with open("design.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
if not tile.startswith('CLK_HROW'):
continue
pip_prefix, pip = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
rows = set(range(clk_table.CLK_TABLE_NUM_ROWS))
columns = set(range(clk_table.CLK_TABLE_NUM_COLS))
if src in table:
row, column = table[src]
segmk.add_tile_tag(tile,
'{}.HCLK_ENABLE_ROW{}'.format(dst, row), 1)
segmk.add_tile_tag(
tile, '{}.HCLK_ENABLE_COLUMN{}'.format(dst, column), 1)
rows.remove(row)
columns.remove(column)
for row in rows:
segmk.add_tile_tag(tile,
'{}.HCLK_ENABLE_ROW{}'.format(dst,
row), 0)
for column in columns:
segmk.add_tile_tag(
tile, '{}.HCLK_ENABLE_COLUMN{}'.format(dst, column), 0)
if tile not in active_clks:
active_clks[tile] = set()
active_clks[tile].add(src)
if 'GCLK' in src:
if src not in active_gclks:
active_gclks[src] = set()
active_gclks[src].add(tile)
tiles = sorted(active_clks.keys())
for tile in active_clks:
for src in table:
if 'GCLK' not in src:
active = src in active_clks[tile]
segmk.add_tile_tag(tile, '{}_ACTIVE'.format(src), active)
else:
if src not in active_gclks:
segmk.add_tile_tag(tile, '{}_ACTIVE'.format(src), 0)
elif tile in active_gclks[src]:
segmk.add_tile_tag(tile, '{}_ACTIVE'.format(src), 1)
segmk.compile()
segmk.write()
tiledata[tile] = {
"pips": set(),
"nodes": set(),
}
if ab == "A":
tiledata[tile]["pips"].add((dst, src))
pipdata.add((dst, src))
else:
tiledata[tile]["nodes"].add(src)
tiledata[tile]["nodes"].add(dst)
for tile, pips_nodes in tiledata.items():
pips = pips_nodes["pips"]
nodes = pips_nodes["nodes"]
for dst, src in pipdata:
if (dst, src) in pips:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
elif dst not in nodes and src not in nodes:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
def bitfilter(frame_idx, bit_idx):
assert os.getenv("XRAY_DATABASE") in ["artix7", "kintex7"]
return frame_idx in [0, 1]
segmk.compile(bitfilter=bitfilter)
segmk.write(allow_empty=True)
def main():
segmk = Segmaker("design.bits")
designdata = {}
tiledata = {}
pipdata = {}
ppipdata = {}
ignpip = set()
all_clks = {}
piplists = ['cmt_top_l_lower_b.txt', 'cmt_top_r_lower_b.txt']
wirelists = ['cmt_top_l_lower_b_wires.txt', 'cmt_top_r_lower_b_wires.txt']
ppiplists = ['ppips_cmt_top_l_lower_b.db', 'ppips_cmt_top_r_lower_b.db']
# Load PIP lists
print("Loading PIP lists...")
for piplist in piplists:
with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'cmt_top_lower', piplist)) as f:
for l in f:
pip, is_directional = l.strip().split(' ')
tile_type, dst, src = pip.split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
all_clks[tile_type] = set()
pipdata[tile_type].append((src, dst))
if dst.split('_')[-1].startswith('CLK'):
all_clks[tile_type].add(src)
if not int(is_directional):
pipdata[tile_type].append((dst, src))
if src.split('_')[-1].startswith('CLK'):
all_clks[tile_type].add(dst)
wiredata = {}
for wirelist in wirelists:
with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'cmt_top_lower', wirelist)) as f:
for l in f:
tile_type, wire = l.strip().split()
if tile_type not in wiredata:
wiredata[tile_type] = set()
wiredata[tile_type].add(wire)
# Load PPIP lists (to exclude them)
print("Loading PPIP lists...")
for ppiplist in ppiplists:
fname = os.path.join(
os.getenv('FUZDIR'), '..', '071-ppips', 'build', ppiplist)
with open(fname, 'r') as f:
for l in f:
pip_data, pip_type = l.strip().split()
if pip_type != 'always':
continue
tile_type, dst, src = pip_data.split('.')
if tile_type not in ppipdata:
ppipdata[tile_type] = []
ppipdata[tile_type].append((src, dst))
# Load desgin data
print("Loading design data...")
with open("design.txt", "r") as f:
for line in f:
fields = line.strip().split(",")
designdata[fields[0]] = fields[1:]
with open("design_pips.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
if not tile.startswith('CMT_TOP'):
continue
if 'UPPER_B' in tile:
continue
if 'LOWER_T' in tile:
continue
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set(),
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
#if dst.startswith('CMT_TOP_R_LOWER_B_CLK') or \
# dst.startswith('CMT_TOP_L_LOWER_B_CLK'):
# ignpip.add((src, dst))
active_wires = {}
with open("design_wires.txt", "r") as f:
for l in f:
tile, wire = l.strip().split('/')
if tile not in active_wires:
active_wires[tile] = set()
active_wires[tile].add(wire)
tags = {}
# Populate IN_USE tags
for tile, (site, in_use) in designdata.items():
if tile not in tags:
tags[tile] = {}
tile_type = tile.rsplit("_", maxsplit=1)[0]
tags[tile]["IN_USE"] = int(in_use)
# Populate PIPs
active_clks = {}
for tile in tags.keys():
tile_type = tile.rsplit("_", maxsplit=1)[0]
in_use = tags[tile]["IN_USE"]
if not in_use:
active_pips = []
else:
active_pips = tiledata[tile]["pips"]
for src, dst in pipdata[tile_type]:
if (src, dst) in ignpip:
continue
if (src, dst) in ppipdata[tile_type]:
continue
tag = "{}.{}".format(merge_lr_wires(dst), merge_lr_wires(src))
val = in_use if (src, dst) in active_pips else False
if not (in_use and not val):
if tile not in active_clks:
active_clks[tile] = set()
active_clks[tile].add(src)
tags[tile][tag] = int(val)
for wire in wiredata[tile_type]:
if 'CLK' not in wire:
continue
if 'CLKOUT' in wire:
continue
if 'CLKFB' in wire:
continue
if 'REBUF' in wire:
continue
wire = merge_lr_wires(wire)
if tile not in active_wires:
active_wires[tile] = set()
segmk.add_tile_tag(
tile, '{}_ACTIVE'.format(wire), wire in active_wires[tile])
# Output tags
for tile, tile_tags in tags.items():
for t, v in tile_tags.items():
segmk.add_tile_tag(tile, t, v)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
designdata = {}
tiledata = {}
pipdata = {}
ppipdata = {}
ignpip = set()
piplists = ['cmt_top_l_upper_t.txt', 'cmt_top_r_upper_t.txt']
ppiplists = ['ppips_cmt_top_l_upper_t.db', 'ppips_cmt_top_r_upper_t.db']
# Load PIP lists
print("Loading PIP lists...")
for piplist in piplists:
with open(
os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'cmt_top', piplist)) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
pipdata[tile_type].append((src, dst))
# Load PPIP lists (to exclude them)
print("Loading PPIP lists...")
for ppiplist in ppiplists:
fname = os.path.join(os.getenv('FUZDIR'), '..', '071-ppips', 'build',
ppiplist)
with open(fname, 'r') as f:
for l in f:
pip_data, pip_type = l.strip().split()
if pip_type != 'always':
continue
tile_type, dst, src = pip_data.split('.')
if tile_type not in ppipdata:
ppipdata[tile_type] = []
ppipdata[tile_type].append((src, dst))
# Load desgin data
print("Loading design data...")
with open("design.txt", "r") as f:
for line in f:
fields = line.strip().split(",")
designdata[fields[0]] = fields[1:]
with open("design_pips.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
if not tile.startswith('CMT_TOP'):
continue
if 'UPPER_B' in tile:
continue
if 'LOWER_T' in tile:
continue
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set(),
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
if dst.startswith('CMT_TOP_R_UPPER_T_CLK') or \
dst.startswith('CMT_TOP_L_UPPER_T_CLK'):
ignpip.add((src, dst))
tags = {}
# Populate IN_USE tags
for tile, (site, in_use) in designdata.items():
if tile not in tags:
tags[tile] = {}
tags[tile]["IN_USE"] = int(in_use)
# Populate PIPs
for tile in tags.keys():
tile_type = tile.rsplit("_", maxsplit=1)[0]
in_use = tags[tile]["IN_USE"]
internal_feedback = False
if not in_use:
active_pips = []
else:
active_pips = tiledata[tile]["pips"]
for src, dst in pipdata[tile_type]:
if (src, dst) in ignpip:
continue
if (src, dst) in ppipdata[tile_type]:
continue
tag = "{}.{}".format(dst, src)
val = in_use if (src, dst) in active_pips else False
if not (in_use and not val):
tags[tile][tag] = int(val)
# Output tags
for tile, tile_tags in tags.items():
for t, v in tile_tags.items():
segmk.add_tile_tag(tile, t, v)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
tiledata = {}
pipdata = {}
ignpip = set()
with open(
os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'cmt_top', 'cmt_top_l_upper_t.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
pipdata[tile_type].append((src, dst))
with open(
os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'cmt_top', 'cmt_top_r_upper_t.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
pipdata[tile_type].append((src, dst))
print("Loading tags from design.txt.")
with open("design.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
if not tile.startswith('CMT_TOP'):
continue
if 'UPPER_B' in tile:
continue
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set(),
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
if dst.startswith('CMT_TOP_R_UPPER_T_CLK') or \
dst.startswith('CMT_TOP_L_UPPER_T_CLK'):
ignpip.add((src, dst))
for tile, pips_srcs_dsts in tiledata.items():
tile_type = pips_srcs_dsts["type"]
pips = pips_srcs_dsts["pips"]
for src, dst in pipdata[tile_type]:
if (src, dst) in ignpip:
pass
elif (src, dst) in pips:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
elif (src, dst) not in tiledata[tile]["pips"]:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
internal_feedback = False
for src, dst in [
('CMT_TOP_L_CLKFBOUT2IN', 'CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN'),
('CMT_TOP_R_CLKFBOUT2IN', 'CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN'),
]:
if (src, dst) in pips:
internal_feedback = True
segmk.add_tile_tag(tile, "EXTERNAL_FEEDBACK", not internal_feedback)
segmk.compile(bitfilter=bitfilter)
segmk.write()
