def catboard_blinky_host(clock, led, uart_tx, uart_rx):
"""
The LEDs are controlled from the RPi over the UART
to the FPGA.
"""
glbl = Global(clock, None)
ledreg = Signal(intbv(0)[8:])
# create the timer tick instance
tick_inst = glbl_timer_ticks(glbl, include_seconds=True)
# create the interfaces to the UART
fbustx = FIFOBus(width=8, size=4)
fbusrx = FIFOBus(width=8, size=4)
uart_fifo = FIFOBus(width=8, size=4)
# create the memmap (CSR) interface
memmap = Barebone(glbl, data_width=32, address_width=32)
# create the UART instance.
uart_inst = uartlite(glbl, uart_fifo,
serial_in=uart_rx,
serial_out=uart_tx)
#map uart_fifo to separate readpath and writepath
assign_rw = uart_fifo.assign_read_write_paths(fbusrx,fbustx)
# create the packet command instance
cmd_inst = command_bridge(glbl, fbusrx, fbustx, memmap)
@always_seq(clock.posedge, reset=None)
def beh_led_control():
memmap.done.next = not (memmap.write or memmap.read)
if memmap.write and memmap.mem_addr == 0x20:
ledreg.next = memmap.write_data
@always_comb
def beh_led_read():
if memmap.read and memmap.mem_addr == 0x20:
memmap.read_data.next = ledreg
else:
memmap.read_data.next = 0
# blink one of the LEDs
tone = Signal(intbv(0)[8:])
@always_seq(clock.posedge, reset=None)
def beh_assign():
if glbl.tick_sec:
tone.next = (~tone) & 0x1
led.next = ledreg | tone[5:]
return (tick_inst, uart_inst, cmd_inst, assign_rw,
beh_led_control, beh_led_read, beh_assign)
def icestick_blinky_host(clock, led, pmod, uart_tx, uart_rx,
uart_dtr, uart_rts):
"""
This example is similar to the other examples in this directory but
the LEDs are controlled externally via command packets sent from a
host via the UART on the icestick.
Ports:
clock:
led:
pmod:
uart_tx:
uart_rx:
"""
glbl = Global(clock, None)
ledreg = Signal(intbv(0)[8:])
# create the timer tick instance
tick_inst = glbl_timer_ticks(glbl, include_seconds=True)
# create the interfaces to the UART
fbustx = FIFOBus(width=8, size=4)
fbusrx = FIFOBus(width=8, size=4)
uart_fifo = FIFOBus(width=8, size=4)
# create the memmap (CSR) interface
memmap = Barebone(glbl, data_width=32, address_width=32)
# create the UART instance.
uart_inst = uartlite(glbl, uart_fifo, uart_rx, uart_tx)
#map uart_fifo to separate readpath and writepath
assign_rw = uart_fifo.assign_read_write_paths(fbusrx,fbustx)
# create the packet command instance
cmd_inst = command_bridge(glbl, fbusrx, fbustx, memmap)
@always_seq(clock.posedge, reset=None)
def beh_led_control():
memmap.done.next = not (memmap.write or memmap.read)
if memmap.write and memmap.mem_addr == 0x20:
ledreg.next = memmap.write_data
@always_comb
def beh_led_read():
if memmap.read and memmap.mem_addr == 0x20:
memmap.read_data.next = ledreg
else:
memmap.read_data.next = 0
# blink one of the LEDs
tone = Signal(intbv(0)[8:])
@always_seq(clock.posedge, reset=None)
def beh_assign():
if glbl.tick_sec:
tone.next = (~tone) & 0x1
led.next = ledreg | tone[5:]
pmod.next = 0
# @todo: PMOD OLED memmap control
return (tick_inst, uart_inst, assign_rw, cmd_inst,
beh_led_control, beh_led_read, beh_assign)
