Verify that all example run scripts work correctly """ import sys from os import environ from pathlib import Path from subprocess import call import unittest import pytest from vunit.sim_if.common import has_simulator, simulator_check ROOT = Path(__file__).parent.parent.parent @unittest.skipIf( not has_simulator() or simulator_check(lambda simclass: not simclass.supports_vhpi()), "A simulator/backend that supports interfacing with external C code is required", ) class TestExamples(unittest.TestCase): """ Verify that example projects run correctly """ def setUp(self): self.output_path = str(Path(__file__).parent / "examples_run_out") self.report_file = str(Path(self.output_path) / "xunit.xml") def check(self, run_file, args=None, vhdl_standard="2008", exit_code=0): """ Run external run file and verify exit code """
""" Acceptance test of VUnit end to end functionality """ import unittest from pathlib import Path from os import environ from subprocess import call import sys from tests.common import check_report from vunit.sim_if.common import has_simulator, simulator_is ROOT = Path(__file__).parent @unittest.skipUnless(has_simulator(), "Requires simulator") class TestVunitArtificial(unittest.TestCase): """ Acceptance test of VUnit end to end functionality using artificial test benches. """ def setUp(self): if simulator_is("activehdl"): self.output_path = str(ROOT / "artificial_out") else: # Spaces in path intentional to verify that it is supported self.output_path = str(ROOT / "artificial _out") self.report_file = str(Path(self.output_path) / "xunit.xml") self.artificial_run_vhdl = str(ROOT / "artificial" / "vhdl" / "run.py") self.artificial_run_verilog = str(ROOT / "artificial" / "verilog" /
from vunit import ROOT as RSTR from vunit.builtins import VHDL_PATH from vunit.sim_if.common import has_simulator, simulator_is, simulator_check ROOT = Path(RSTR) def simulator_supports_verilog(): """ Returns True if simulator supports Verilog """ return simulator_is("modelsim", "incisive") # pylint: disable=too-many-public-methods @mark.skipif(not has_simulator(), reason="Requires simulator") class TestExternalRunScripts(TestCase): """ Verify that example projects run correctly """ @mark.skipif(not simulator_supports_verilog(), reason="Requires a Verilog simulator") def test_verilog_user_guide_example_project(self): self.check(ROOT / "examples/verilog/user_guide/run.py", exit_code=1) check_report( self.report_file, [ ("passed", "lib.tb_example_basic.all"), ("passed", "lib.tb_example.Test that a successful test case passes"), ( "failed",