def ANDimm(self, DR, SR, Simm): self.debug('ANDimm R' + str(DR) + ' <- R' + str(SR) + ' & Imm(' + str(Tools.intCom(Simm.data)) + ')') self.gRegs[DR] = self.gRegs[SR].AND(Simm) self.setCC(DR)
def intCom(self): return Tools.intCom(self.data)
def readRegCom(self, index): return Tools.intCom(self.gRegs[index].bin()[1:])