Esempio n. 1
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 def __init__(self, proj):
     """
     Create the main Z80 Disassembler, Creates two OpcodeDispatchers (main and cb)
     Main are all 1-byte opcodes and cb are the 2 byte opcodes
     Initialises cache and next_addr_cache, although not sure the difference between the 2 caches yet
     :param proj:
     """
     self.proj = proj
     self.main = OpcodeDispatcher(main_ops.splitlines())
     self.cb = OpcodeDispatcher(cb_ops.splitlines())
     self.cache = dict()
     self.next_addr_cache = dict()
Esempio n. 2
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class Z80Disasm(object):
    def __init__(self, proj):
        self.proj = proj
        self.main = OpcodeDispatcher(main_ops.splitlines())
        self.cb = OpcodeDispatcher(cb_ops.splitlines())
        self.cache = dict()
        self.next_addr_cache = dict()

    def _decode(self, addr):
        opcode = self.proj.rom.get(addr)
        if opcode == 0xCB:
            return self.cb.decode(self.proj, addr.offset(1))
        else:
            return self.main.decode(self.proj, addr)

    def decodeCache(self, addr):
        if addr not in self.cache:
            self.cache[addr], self.next_addr_cache[addr] = self._decode(addr)
        return self.cache[addr], self.next_addr_cache[addr]
Esempio n. 3
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class Z80Disasm(object):
    def __init__(self, proj):
        self.proj = proj
        self.main = OpcodeDispatcher(main_ops.splitlines())
        self.cb = OpcodeDispatcher(cb_ops.splitlines())
        self.cache = dict()
        self.next_addr_cache = dict()

    def _decode(self, addr):
        opcode = self.proj.rom.get(addr)
        if opcode == 0xCB:
            return self.cb.decode(self.proj, addr.offset(1))
        else:
            return self.main.decode(self.proj, addr)

    def decodeCache(self, addr):
        if addr not in self.cache:
            self.cache[addr], self.next_addr_cache[addr] = self._decode(addr)
        return self.cache[addr], self.next_addr_cache[addr]
Esempio n. 4
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class Z80Disasm(object):
    def __init__(self, proj):
        """
        Create the main Z80 Disassembler, Creates two OpcodeDispatchers (main and cb)
        Main are all 1-byte opcodes and cb are the 2 byte opcodes
        Initialises cache and next_addr_cache, although not sure the difference between the 2 caches yet
        :param proj:
        """
        self.proj = proj
        self.main = OpcodeDispatcher(main_ops.splitlines())
        self.cb = OpcodeDispatcher(cb_ops.splitlines())
        self.cache = dict()
        self.next_addr_cache = dict()

    def _decode(self, addr):
        """
        Decode the opcode at the addr specified, if the opcode value at addr is 0xCB then decode from the CB Dispatcher,
        otherwise decode from the main Dispatcher.
        :param addr:
        :return:
        """
        opcode = self.proj.rom.get(addr)
        if opcode == 0xCB:
            return self.cb.decode(self.proj, addr.offset(1))
        else:
            return self.main.decode(self.proj, addr)

    def decodeCache(self, addr):
        """
        Decode the opcode at the address specified using the cache to see if it has already been decoded previously,
        saving the work of decoding every single time!
        :param addr:
        :return:
        """
        if addr not in self.cache:
            self.cache[addr], self.next_addr_cache[addr] = self._decode(addr)
        return self.cache[addr], self.next_addr_cache[addr]
Esempio n. 5
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 def __init__(self, proj):
     self.proj = proj
     self.main = OpcodeDispatcher(main_ops.splitlines())
     self.cb = OpcodeDispatcher(cb_ops.splitlines())
     self.cache = dict()
     self.next_addr_cache = dict()
Esempio n. 6
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 def __init__(self, proj):
     self.proj = proj
     self.main = OpcodeDispatcher(main_ops.splitlines())
     self.cb = OpcodeDispatcher(cb_ops.splitlines())
     self.cache = dict()
     self.next_addr_cache = dict()