def i_add(self, op):
dst = self.getOperValue(op, 0)
src = self.getOperValue(op, 1)
dsize = op.opers[0].tsize
ssize = op.opers[1].tsize
#FIXME PDE and flags
if dst == None or src == None:
self.undefFlags()
self.setOperValue(op, 0, None)
return
if dsize > ssize:
src = e_bits.sign_extend(src, ssize, dsize)
ssize = dsize
udst = e_bits.unsigned(dst, dsize)
usrc = e_bits.unsigned(src, ssize)
sdst = e_bits.signed(dst, dsize)
ssrc = e_bits.signed(src, ssize)
ures = udst + usrc
sres = sdst + ssrc
self.setFlag(EFLAGS_CF, e_bits.is_unsigned_carry(ures, dsize))
self.setFlag(EFLAGS_PF, e_bits.is_parity_byte(ures))
self.setFlag(EFLAGS_AF, e_bits.is_aux_carry(src, dst))
self.setFlag(EFLAGS_ZF, not ures)
self.setFlag(EFLAGS_SF, e_bits.is_signed(ures, dsize))
self.setFlag(EFLAGS_OF, e_bits.is_signed_overflow(sres, dsize))
self.setOperValue(op, 0, ures)
def intSubBase(self, src1, src2, Sflag=0, rd=0):
# So we can either do a BUNCH of crazyness with xor and shifting to
# get the necessary flags here, *or* we can just do both a signed and
# unsigned sub and use the results.
udst = e_bits.unsigned(src1, 4)
usrc = e_bits.unsigned(src2, 4)
sdst = e_bits.signed(src1, 4)
ssrc = e_bits.signed(src2, 4)
ures = udst - usrc
sres = sdst - ssrc
if Sflag:
curmode = self.getProcMode()
if rd == 15:
if(curmode != PM_sys and curmode != PM_usr):
self.setCPSR(self.getSPSR(curmode))
else:
raise Exception("Messed up opcode... adding to r15 from PM_usr or PM_sys")
self.setFlag(PSR_N_bit, e_bits.is_signed(ures, 4))
self.setFlag(PSR_Z_bit, not ures)
self.setFlag(PSR_C_bit, not e_bits.is_unsigned_carry(ures, 4))
self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(sres, 4))
return ures
def i_adc(self, op):
dst = self.getOperValue(op, 0)
src = self.getOperValue(op, 1)
# PDE
if dst == None or src == None:
self.undefFlags()
self.setOperValue(op, 0, None)
return
cf = 0
if self.getFlag(EFLAGS_CF):
cf = 1
dstsize = op.opers[0].tsize
srcsize = op.opers[1].tsize
if (isinstance(op.opers[1], i386ImmOper) and
srcsize < dstsize):
src = e_bits.sign_extend(src, srcsize, dstsize)
srcsize = dstsize
#FIXME perhaps unify the add/adc flags/arith code
res = dst + src + cf
tsize = op.opers[0].tsize
self.setFlag(EFLAGS_CF, e_bits.is_unsigned_carry(res, tsize))
self.setFlag(EFLAGS_PF, e_bits.is_parity_byte(res))
self.setFlag(EFLAGS_AF, e_bits.is_aux_carry(src, dst))
self.setFlag(EFLAGS_ZF, not res)
self.setFlag(EFLAGS_SF, e_bits.is_signed(res, tsize))
self.setFlag(EFLAGS_OF, e_bits.is_signed_overflow(res, tsize))
self.setOperValue(op, 0, res)
def i_adc(self, op):
dst = self.getOperValue(op, 0)
src = self.getOperValue(op, 1)
# PDE
if dst == None or src == None:
self.undefFlags()
self.setOperValue(op, 0, None)
return
cf = 0
if self.getFlag(EFLAGS_CF):
cf = 1
dstsize = op.opers[0].tsize
srcsize = op.opers[1].tsize
if (isinstance(op.opers[1], i386ImmOper) and
srcsize < dstsize):
src = e_bits.sign_extend(src, srcsize, dstsize)
srcsize = dstsize
#FIXME perhaps unify the add/adc flags/arith code
res = dst + src + cf
tsize = op.opers[0].tsize
self.setFlag(EFLAGS_CF, e_bits.is_unsigned_carry(res, tsize))
self.setFlag(EFLAGS_PF, e_bits.is_parity_byte(res))
self.setFlag(EFLAGS_AF, e_bits.is_aux_carry(src, dst))
self.setFlag(EFLAGS_ZF, not res)
self.setFlag(EFLAGS_SF, e_bits.is_signed(res, tsize))
self.setFlag(EFLAGS_OF, e_bits.is_signed_overflow(res, tsize))
self.setOperValue(op, 0, res)
def i_eor(self, op):
src1 = self.getOperValue(op, 1)
src2 = self.getOperValue(op, 2)
#FIXME PDE and flags
if src1 == None or src2 == None:
self.undefFlags()
self.setOperValue(op, 0, None)
return
usrc1 = e_bits.unsigned(src1, 4)
usrc2 = e_bits.unsigned(src2, 4)
ures = usrc1 ^ usrc2
self.setOperValue(op, 0, ures)
curmode = self.getProcMode()
if op.iflags & IF_S:
if op.opers[0].reg == 15:
if (curmode != PM_sys and curmode != PM_usr):
self.setCPSR(self.getSPSR(curmode))
else:
raise Exception("Messed up opcode... adding to r15 from PM_usr or PM_sys")
self.setFlag(PSR_C_bit, e_bits.is_unsigned_carry(ures, 4))
self.setFlag(PSR_Z_bit, not ures)
self.setFlag(PSR_N_bit, e_bits.is_signed(ures, 4))
self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(sres, 4))
def i_adc(self, op):
dst = self.getOperValue(op, 0)
src = self.getOperValue(op, 1)
cf = 0
if self.getFlag(EFLAGS_CF):
cf = 1
dsize = op.opers[0].tsize
ssize = op.opers[1].tsize
sdst = e_bits.signed(dst, dsize)
ssrc = e_bits.signed(src, ssize)
if (isinstance(op.opers[1], i386ImmOper) and ssize < dsize):
src = e_bits.sign_extend(src, ssize, dsize)
ssize = dsize
#FIXME perhaps unify the add/adc flags/arith code
res = dst + src + cf
sres = sdst + ssrc + cf
tsize = op.opers[0].tsize
self.setFlag(EFLAGS_CF, e_bits.is_unsigned_carry(res, tsize))
self.setFlag(EFLAGS_PF, e_bits.is_parity_byte(res))
self.setFlag(EFLAGS_AF, e_bits.is_aux_carry(src, dst))
self.setFlag(EFLAGS_ZF, not res)
self.setFlag(EFLAGS_SF, e_bits.is_signed(res, tsize))
self.setFlag(EFLAGS_OF, e_bits.is_signed_overflow(sres, dsize))
self.setOperValue(op, 0, res)
def i_adc(self, op):
dst = self.getOperValue(op, 0)
src = self.getOperValue(op, 1)
cf = 0
if self.getFlag(EFLAGS_CF):
cf = 1
dsize = op.opers[0].tsize
ssize = op.opers[1].tsize
sdst = e_bits.signed(dst, dsize)
ssrc = e_bits.signed(src, ssize)
if (isinstance(op.opers[1], i386ImmOper) and
ssize < dsize):
src = e_bits.sign_extend(src, ssize, dsize)
ssize = dsize
#FIXME perhaps unify the add/adc flags/arith code
res = dst + src + cf
sres = sdst + ssrc + cf
tsize = op.opers[0].tsize
self.setFlag(EFLAGS_CF, e_bits.is_unsigned_carry(res, tsize))
self.setFlag(EFLAGS_PF, e_bits.is_parity_byte(res))
self.setFlag(EFLAGS_AF, e_bits.is_aux_carry(src, dst))
self.setFlag(EFLAGS_ZF, not res)
self.setFlag(EFLAGS_SF, e_bits.is_signed(res, tsize))
self.setFlag(EFLAGS_OF, e_bits.is_signed_overflow(sres, dsize))
self.setOperValue(op, 0, res)
def i_add(self, op):
dst = self.getOperValue(op, 0)
src = self.getOperValue(op, 1)
dsize = op.opers[0].tsize
ssize = op.opers[1].tsize
if dsize > ssize:
src = e_bits.sign_extend(src, ssize, dsize)
ssize = dsize
udst = e_bits.unsigned(dst, dsize)
usrc = e_bits.unsigned(src, ssize)
sdst = e_bits.signed(dst, dsize)
ssrc = e_bits.signed(src, ssize)
ures = udst + usrc
sres = sdst + ssrc
self.setFlag(EFLAGS_CF, e_bits.is_unsigned_carry(ures, dsize))
self.setFlag(EFLAGS_PF, e_bits.is_parity_byte(ures))
self.setFlag(EFLAGS_AF, e_bits.is_aux_carry(src, dst))
self.setFlag(EFLAGS_ZF, not ures)
self.setFlag(EFLAGS_SF, e_bits.is_signed(ures, dsize))
self.setFlag(EFLAGS_OF, e_bits.is_signed_overflow(sres, dsize))
self.setOperValue(op, 0, ures)
def intSubBase(self, src1, src2, Sflag=0, rd=0):
# So we can either do a BUNCH of crazyness with xor and shifting to
# get the necessary flags here, *or* we can just do both a signed and
# unsigned sub and use the results.
udst = e_bits.unsigned(src1, 4)
usrc = e_bits.unsigned(src2, 4)
sdst = e_bits.signed(src1, 4)
ssrc = e_bits.signed(src2, 4)
ures = udst - usrc
sres = sdst - ssrc
if Sflag:
curmode = self.getProcMode()
if rd == 15:
if curmode != PM_sys and curmode != PM_usr:
self.setCPSR(self.getSPSR(curmode))
else:
raise Exception(
"Messed up opcode... adding to r15 from PM_usr or PM_sys"
)
self.setFlag(PSR_N_bit, e_bits.is_signed(ures, 4))
self.setFlag(PSR_Z_bit, not ures)
self.setFlag(PSR_C_bit, e_bits.is_unsigned_carry(ures, 4))
self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(sres, 4))
return ures
def i_eor(self, op):
src1 = self.getOperValue(op, 1)
src2 = self.getOperValue(op, 2)
# FIXME PDE and flags
if src1 == None or src2 == None:
self.undefFlags()
self.setOperValue(op, 0, None)
return
usrc1 = e_bits.unsigned(src1, 4)
usrc2 = e_bits.unsigned(src2, 4)
ures = usrc1 ^ usrc2
self.setOperValue(op, 0, ures)
curmode = self.getProcMode()
if op.iflags & IF_S:
if op.opers[0].reg == 15:
if (curmode != PM_sys and curmode != PM_usr):
self.setCPSR(self.getSPSR(curmode))
else:
raise Exception(
"Messed up opcode... adding to r15 from PM_usr or PM_sys"
)
self.setFlag(PSR_C_bit, e_bits.is_unsigned_carry(ures, 4))
self.setFlag(PSR_Z_bit, not ures)
self.setFlag(PSR_N_bit, e_bits.is_signed(ures, 4))
self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(sres, 4))
def doFlags(self, flagtup):
(ssize, dsize, sres, ures, sdst, udst) = flagtup
self.setFlag(h8_regs.CCR_H, e_bits.is_signed_half_carry(ures, dsize, udst))
self.setFlag(h8_regs.CCR_C, e_bits.is_unsigned_carry(ures, dsize))
self.setFlag(h8_regs.CCR_Z, not ures)
self.setFlag(h8_regs.CCR_N, e_bits.is_signed(ures, dsize))
self.setFlag(h8_regs.CCR_V, e_bits.is_signed_overflow(sres, dsize))
def i_imul(self, op):
#FIXME eflags
# FIXME imul bugs
ocount = len(op.opers)
if ocount == 2:
dst = self.getOperValue(op, 0)
src = self.getOperValue(op, 1)
dsize = op.opers[0].tsize
ssize = op.opers[1].tsize
# FIXME all these are taken care of in disasm now...
if dsize > ssize:
src = e_bits.sign_extend(src, ssize, dsize)
ssize = dsize
res = dst * src
sof = e_bits.is_unsigned_carry(res, dsize)
self.setFlag(EFLAGS_CF, sof)
self.setFlag(EFLAGS_OF, sof)
self.setOperValue(op, 0, res)
elif ocount == 3:
dst = self.getOperValue(op, 0)
src1 = self.getOperValue(op, 1)
src2 = self.getOperValue(op, 2)
dsize = op.opers[0].tsize
ssize1 = op.opers[1].tsize
ssize2 = op.opers[2].tsize
if dsize > ssize2: # Only the last operand may be shorter imm
src2 = e_bits.sign_extend(src2, ssize2, dsize)
ssize2 = dsize
res = src1 * src2
sof = e_bits.is_unsigned_carry(res, dsize)
self.setFlag(EFLAGS_CF, sof)
self.setFlag(EFLAGS_OF, sof)
self.setOperValue(op, 0, res)
else:
raise envi.UnsupportedInstruction(self, op)
def doFlags(self, flagtup):
(ssize, dsize, sres, ures, sdst, udst) = flagtup
self.setFlag(CCR_H, e_bits.is_signed_half_carry(ures, dsize, udst))
self.setFlag(CCR_C, e_bits.is_unsigned_carry(ures, dsize))
self.setFlag(CCR_Z, not ures)
self.setFlag(CCR_N, e_bits.is_signed(ures, dsize))
self.setFlag(CCR_V, e_bits.is_signed_overflow(sres, dsize))
def i_imul(self, op):
#FIXME eflags
# FIXME imul bugs
ocount = len(op.opers)
if ocount == 2:
dst = self.getOperValue(op, 0)
src = self.getOperValue(op, 1)
dsize = op.opers[0].tsize
ssize = op.opers[1].tsize
# FIXME all these are taken care of in disasm now...
if dsize > ssize:
src = e_bits.sign_extend(src, ssize, dsize)
ssize = dsize
res = dst * src
sof = e_bits.is_unsigned_carry(res, dsize)
self.setFlag(EFLAGS_CF, sof)
self.setFlag(EFLAGS_OF, sof)
self.setOperValue(op, 0, res)
elif ocount == 3:
dst = self.getOperValue(op, 0)
src1 = self.getOperValue(op, 1)
src2 = self.getOperValue(op, 2)
dsize = op.opers[0].tsize
ssize1 = op.opers[1].tsize
ssize2 = op.opers[2].tsize
if dsize > ssize2: # Only the last operand may be shorter imm
src2 = e_bits.sign_extend(src2, ssize2, dsize)
ssize2 = dsize
res = src1 * src2
sof = e_bits.is_unsigned_carry(res, dsize)
self.setFlag(EFLAGS_CF, sof)
self.setFlag(EFLAGS_OF, sof)
self.setOperValue(op, 0, res)
else:
raise envi.UnsupportedInstruction(self, op)
def i_teq(self, op):
src1 = self.getOperValue(op, 0)
src2 = self.getOperValue(op, 1)
dsize = op.opers[0].tsize
ures = src1 ^ src2
self.setFlag(PSR_N_bit, e_bits.is_signed(ures, dsize))
self.setFlag(PSR_Z_bit, (0, 1)[ures == 0])
self.setFlag(PSR_C_bit, e_bits.is_unsigned_carry(ures, dsize))
def i_tst(self, op):
src1 = self.getOperValue(op, 0)
src2 = self.getOperValue(op, 1)
dsize = op.opers[0].tsize
ures = src1 & src2
self.setFlag(PSR_N_bit, e_bits.is_signed(ures, dsize))
self.setFlag(PSR_Z_bit, (0,1)[ures==0])
self.setFlag(PSR_C_bit, e_bits.is_unsigned_carry(ures, dsize))
def i_add(self, op):
(ssize, dsize, sres, ures, sdst, udst) = self.integerAddition(op)
self.setOperValue(op, 1, ures)
# FIXME: test and validate
self.setFlag(CCR_H, e_bits.is_signed_half_carry(sres, dsize, sdst))
self.setFlag(CCR_C, e_bits.is_unsigned_carry(ures, dsize))
self.setFlag(CCR_Z, not ures)
self.setFlag(CCR_N, e_bits.is_signed(ures, dsize))
self.setFlag(CCR_V, e_bits.is_signed_overflow(sres, dsize))
def i_add(self, op):
(ssize, dsize, sres, ures, sdst, udst) = self.integerAddition(op)
self.setOperValue(op, 1, ures)
# FIXME: test and validate
self.setFlag(h8_regs.CCR_H, e_bits.is_signed_half_carry(sres, dsize, sdst))
self.setFlag(h8_regs.CCR_C, e_bits.is_unsigned_carry(ures, dsize))
self.setFlag(h8_regs.CCR_Z, not ures)
self.setFlag(h8_regs.CCR_N, e_bits.is_signed(ures, dsize))
self.setFlag(h8_regs.CCR_V, e_bits.is_signed_overflow(sres, dsize))
def i_orr(self, op):
val1 = self.getOperValue(op, 1)
val2 = self.getOperValue(op, 2)
val = val1 | val2
self.setOperValue(op, 0, val)
Sflag = op.iflags & IF_S # FIXME: IF_PSR_S???
if Sflag:
self.setFlag(PSR_N_bit, e_bits.is_signed(val, 4))
self.setFlag(PSR_Z_bit, not val)
self.setFlag(PSR_C_bit, e_bits.is_unsigned_carry(val, 4))
self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(val, 4))
def i_neg(self, op):
dsize = op.opers[0].tsize
oper = self.getOperValue(op, 0)
oper = e_bits.signed(oper, dsize)
oper = -oper
self.setOperValue(op, 0, oper)
self.setFlag(CCR_H, e_bits.is_signed_half_carry(oper, dsize, oper))
self.setFlag(CCR_N, e_bits.is_signed(oper, dsize))
self.setFlag(CCR_Z, not oper)
self.setFlag(CCR_V, e_bits.is_signed_overflow(oper, dsize))
self.setFlag(CCR_C, e_bits.is_unsigned_carry(oper, dsize))
def i_neg(self, op):
dsize = op.opers[0].tsize
oper = self.getOperValue(op, 0)
oper = e_bits.signed(oper, dsize)
oper = -oper
self.setOperValue(op, 0, oper)
self.setFlag(h8_regs.CCR_H, e_bits.is_signed_half_carry(oper, dsize, oper))
self.setFlag(h8_regs.CCR_N, e_bits.is_signed(oper, dsize))
self.setFlag(h8_regs.CCR_Z, not oper)
self.setFlag(h8_regs.CCR_V, e_bits.is_signed_overflow(oper, dsize))
self.setFlag(h8_regs.CCR_C, e_bits.is_unsigned_carry(oper, dsize))
def i_mul(self, op):
Rn = self.getOperValue(op, 1)
if len(op.opers) == 3:
Rm = self.getOperValue(op, 2)
else:
Rm = self.getOperValue(op, 0)
val = Rn * Rm
self.setOperValue(op, 0, val)
Sflag = op.iflags & IF_S
if Sflag:
self.setFlag(PSR_N_bit, e_bits.is_signed(val, 4))
self.setFlag(PSR_Z_bit, not val)
self.setFlag(PSR_C_bit, e_bits.is_unsigned_carry(val, 4))
self.setFlag(PSR_V_bit, e_bits.is_signed_overflow(val, 4))
def doSubC(self, a, b, carry, size):
ua = e_bits.unsigned(a, size)
ub = e_bits.unsigned(b, size)
sa = e_bits.signed(a, size)
sb = e_bits.signed(b, size)
ures = ua - ub - 1 + carry
sres = sa - sb - 1 + carry
res = e_bits.unsigned(ures, size)
self.setFlag(SR_N, e_bits.msb(res, size))
self.setFlag(SR_Z, res == 0)
self.setFlag(SR_C, not e_bits.is_unsigned_carry(ures, size))
self.setFlag(SR_V, e_bits.is_signed_overflow(sres, size))
return res
def doSubC(self, a, b, carry, size):
ua = e_bits.unsigned(a, size)
ub = e_bits.unsigned(b, size)
sa = e_bits.signed(a, size)
sb = e_bits.signed(b, size)
ures = ua - ub - 1 + carry
sres = sa - sb - 1 + carry
res = e_bits.unsigned(ures, size)
self.setFlag(SR_N, e_bits.msb(res, size))
self.setFlag(SR_Z, res == 0)
self.setFlag(SR_C, not e_bits.is_unsigned_carry(ures, size))
self.setFlag(SR_V, e_bits.is_signed_overflow(sres, size))
return res
def i_xor(self, op):
src1 = self.getOperValue(op, 0)
src2 = self.getOperValue(op, 1)
#FIXME PDE and flags
if src1 == None or src2 == None:
self.undefFlags()
self.setOperValue(op, 1, None)
return
usrc1 = e_bits.unsigned(src1, 4)
usrc2 = e_bits.unsigned(src2, 4)
ures = usrc1 ^ usrc2
self.setOperValue(op, 1, ures)
self.setFlag(CCR_C, e_bits.is_unsigned_carry(ures, 4))
self.setFlag(CCR_Z, not ures)
self.setFlag(CCR_N, e_bits.is_signed(ures, 4))
self.setFlag(CCR_V, e_bits.is_signed_overflow(ures, 4))
def i_xor(self, op):
src1 = self.getOperValue(op, 0)
src2 = self.getOperValue(op, 1)
# FIXME PDE and flags
if src1 is None or src2 is None:
self.undefFlags()
self.setOperValue(op, 1, None)
return
usrc1 = e_bits.unsigned(src1, 4)
usrc2 = e_bits.unsigned(src2, 4)
ures = usrc1 ^ usrc2
self.setOperValue(op, 1, ures)
self.setFlag(h8_regs.CCR_C, e_bits.is_unsigned_carry(ures, 4))
self.setFlag(h8_regs.CCR_Z, not ures)
self.setFlag(h8_regs.CCR_N, e_bits.is_signed(ures, 4))
self.setFlag(h8_regs.CCR_V, e_bits.is_signed_overflow(ures, 4))
def intSubBase(self, src, dst, ssize, dsize):
usrc = e_bits.unsigned(src, ssize)
udst = e_bits.unsigned(dst, dsize)
ssrc = e_bits.signed(src, ssize)
sdst = e_bits.signed(dst, dsize)
ures = udst - usrc
sres = sdst - ssrc
#print "dsize/ssize: %d %d" % (dsize, ssize)
#print "unsigned: %d %d %d" % (usrc, udst, ures)
#print "signed: %d %d %d" % (ssrc, sdst, sres)
self.setFlag(EFLAGS_OF, e_bits.is_signed_overflow(sres, dsize))
self.setFlag(EFLAGS_AF, e_bits.is_aux_carry_sub(usrc, udst))
self.setFlag(EFLAGS_CF, e_bits.is_unsigned_carry(ures, dsize))
self.setFlag(EFLAGS_SF, e_bits.is_signed(ures, dsize))
self.setFlag(EFLAGS_ZF, not sres)
self.setFlag(EFLAGS_PF, e_bits.is_parity_byte(ures))
return ures
def intSubBase(self, src, dst, ssize, dsize):
usrc = e_bits.unsigned(src, ssize)
udst = e_bits.unsigned(dst, dsize)
ssrc = e_bits.signed(src, ssize)
sdst = e_bits.signed(dst, dsize)
ures = udst - usrc
sres = sdst - ssrc
#print "dsize/ssize: %d %d" % (dsize, ssize)
#print "unsigned: %d %d %d" % (usrc, udst, ures)
#print "signed: %d %d %d" % (ssrc, sdst, sres)
self.setFlag(EFLAGS_OF, e_bits.is_signed_overflow(sres, dsize))
self.setFlag(EFLAGS_AF, e_bits.is_aux_carry(usrc, udst))
self.setFlag(EFLAGS_CF, e_bits.is_unsigned_carry(ures, dsize))
self.setFlag(EFLAGS_SF, e_bits.is_signed(ures, dsize))
self.setFlag(EFLAGS_ZF, not sres)
self.setFlag(EFLAGS_PF, e_bits.is_parity_byte(ures))
return ures
def intSubBase(self, src, dst, ssize, dsize):
usrc = e_bits.unsigned(src, ssize)
udst = e_bits.unsigned(dst, dsize)
ssrc = e_bits.signed(src, ssize)
sdst = e_bits.signed(dst, dsize)
ures = udst - usrc
sres = sdst - ssrc
#print "dsize/ssize: %d %d" % (dsize, ssize)
#print "unsigned: %d %d %d" % (usrc, udst, ures)
#print "signed: %d %d %d" % (ssrc, sdst, sres)
"""
http://cnx.org/content/m23497/latest/
Bit Description
8 V Overflow bit.V = 1 -> Result of an arithmetic operation overflows the signed-variable range.
2 N Negative flag.N = 1 -> result of a byte or word operation is negative.
1 Z Zero flag.Z = 1 -> result of a byte or word operation is 0.
0 C Carry flag.C = 1 -> result of a byte or word operation produced a carry.
REG_SR_C = 1 << 0 # Carry bit
REG_SR_Z = 1 << 1
REG_SR_N = 1 << 2
REG_SR_V = 1 << 8
"""
#print "ures: %x udst: %x usrc: %x"% (ures, udst, usrc)
self.setFlag(REG_SR_V, e_bits.is_signed_overflow(sres, dsize))
self.setFlag(REG_SR_Z, not sres)
self.setFlag(REG_SR_N, sres < 0)
#self.setFlag(REG_SR_C, e_bits.is_aux_carry(usrc, udst))
self.setFlag(REG_SR_C, e_bits.is_unsigned_carry(ures, dsize))
return ures
def intSubBase(self, src, dst, ssize, dsize):
usrc = e_bits.unsigned(src, ssize)
udst = e_bits.unsigned(dst, dsize)
ssrc = e_bits.signed(src, ssize)
sdst = e_bits.signed(dst, dsize)
ures = udst - usrc
sres = sdst - ssrc
#print "dsize/ssize: %d %d" % (dsize, ssize)
#print "unsigned: %d %d %d" % (usrc, udst, ures)
#print "signed: %d %d %d" % (ssrc, sdst, sres)
"""
http://cnx.org/content/m23497/latest/
Bit Description
8 V Overflow bit.V = 1 -> Result of an arithmetic operation overflows the signed-variable range.
2 N Negative flag.N = 1 -> result of a byte or word operation is negative.
1 Z Zero flag.Z = 1 -> result of a byte or word operation is 0.
0 C Carry flag.C = 1 -> result of a byte or word operation produced a carry.
REG_SR_C = 1 << 0 # Carry bit
REG_SR_Z = 1 << 1
REG_SR_N = 1 << 2
REG_SR_V = 1 << 8
"""
#print "ures: %x udst: %x usrc: %x"% (ures, udst, usrc)
self.setFlag(REG_SR_V, e_bits.is_signed_overflow(sres, dsize))
self.setFlag(REG_SR_Z, not sres)
self.setFlag(REG_SR_N, sres < 0)
#self.setFlag(REG_SR_C, e_bits.is_aux_carry(usrc, udst))
self.setFlag(REG_SR_C, e_bits.is_unsigned_carry(ures, dsize))
return ures
