Esempio n. 1
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    def __init__(self, ftdi_sync, streaming_sources):

        # CSR Command Decoding
        bdec = BusDecode()
        self.comb += [
                bdec.sink.stb.eq(ftdi_sync.incoming_fifo.readable),
                bdec.sink.payload.d.eq(ftdi_sync.incoming_fifo.dout),
                ftdi_sync.incoming_fifo.re.eq(bdec.sink.ack),
                
                ]
        
        # Bus master
        busmaster = CSR_Master(has_completion=True)
        self.master = busmaster.master

        # Encode output for response
        benc = BusEncode()
        
        # Connect decoder to busmaster to encoder
        g = DataFlowGraph()
        g.add_connection(bdec, busmaster)
        g.add_connection(busmaster, benc)
        self.submodules.fg = CompositeActor(g)

        # Bus interleaver to merge streaming and response packets
        bilv = BusInterleave([benc] + streaming_sources)
        self.submodules += bilv
        self.comb += [
                ftdi_sync.output_fifo.we.eq(bilv.source.stb),
                ftdi_sync.output_fifo.din.eq(bilv.source.payload.d),
                bilv.source.ack.eq(ftdi_sync.output_fifo.writable)
                ]
Esempio n. 2
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    def __init__(self, ftdi_sync, streaming_sources):

        # CSR Command Decoding
        bdec = BusDecode()
        self.comb += [
                bdec.sink.stb.eq(ftdi_sync.incoming_fifo.readable),
                bdec.sink.payload.d.eq(ftdi_sync.incoming_fifo.dout),
                ftdi_sync.incoming_fifo.re.eq(bdec.sink.ack),
                
                ]
        
        # Bus master
        busmaster = CSR_Master(has_completion=True)
        self.master = busmaster.master

        # Encode output for response
        benc = BusEncode()
        
        # Connect decoder to busmaster to encoder
        g = DataFlowGraph()
        g.add_connection(bdec, busmaster)
        g.add_connection(busmaster, benc)
        self.submodules.fg = CompositeActor(g)

        # Bus interleaver to merge streaming and response packets
        bilv = BusInterleave([benc] + streaming_sources)
        self.submodules += bilv
        self.comb += [
                ftdi_sync.output_fifo.we.eq(bilv.source.stb),
                ftdi_sync.output_fifo.din.eq(bilv.source.payload.d),
                bilv.source.ack.eq(ftdi_sync.output_fifo.writable)
                ]
Esempio n. 3
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 def __init__(self, data):
     self.source = SimSource(data)
     unescaper = Unescaper(data_layout)
     self.asink = SimSink("a")
     self.bsink = SimSink("b")
     g = DataFlowGraph()
     g.add_connection(self.source, unescaper)
     g.add_connection(unescaper, self.asink, "source_a")
     g.add_connection(unescaper, self.bsink, "source_b")
     self.submodules.comp = CompositeActor(g)
Esempio n. 4
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    def __init__(self, usb_actor):

        g = DataFlowGraph()

        fifo = SyncFIFO([('d', 16)], 64)
        in_buffer = Relax([('d', 16)])
        out_buffer = Relax([('d', 16)])

        g.add_connection(in_buffer, fifo)
        g.add_connection(fifo, out_buffer)

        g.add_connection(out_buffer, usb_actor)
        g.add_connection(usb_actor, in_buffer)

        self.submodules.composite = CompositeActor(g)
        self.busy = self.composite.busy
Esempio n. 5
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    def __init__(self, usb_actor):

        g = DataFlowGraph()

        fifo = SyncFIFO([('d', 16)], 64)
        in_buffer = Relax([('d', 16)])
        out_buffer = Relax([('d', 16)])

        g.add_connection(in_buffer, fifo)
        g.add_connection(fifo, out_buffer)

        g.add_connection(out_buffer, usb_actor)
        g.add_connection(usb_actor, in_buffer)

        self.submodules.composite = CompositeActor(g)
        self.busy = self.composite.busy
Esempio n. 6
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 def __init__(self, data):
     self.source = SimSource(data)
     unescaper = Unescaper(data_layout)
     self.asink = SimSink("a")
     self.bsink = SimSink("b")
     g = DataFlowGraph()
     g.add_connection(self.source, unescaper)
     g.add_connection(unescaper, self.asink, "source_a")
     g.add_connection(unescaper, self.bsink, "source_b")
     self.submodules.comp = CompositeActor(g)
Esempio n. 7
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    def __init__(self, pads_vga, pads_dvi, *lasmims, blender_latency=5):
        assert(all(lasmim.aw == lasmims[0].aw and lasmim.dw == lasmims[0].dw
            for lasmim in lasmims))
        pack_factor = lasmims[0].dw//bpp

        self.fi = FrameInitiator(lasmims[0].aw, pack_factor, len(lasmims))
        self.blender = Blender(len(lasmims), pack_factor, blender_latency)
        self.driver = Driver(pack_factor, pads_vga, pads_dvi)

        g = DataFlowGraph()
        epixel_layout = pixel_layout(pack_factor)
        for n, lasmim in enumerate(lasmims):
            intseq = misc.IntSequence(lasmim.aw, lasmim.aw)
            dma_out = AbstractActor(plumbing.Buffer)
            g.add_connection(self.fi, intseq, source_subr=self.fi.dma_subr(n))
            g.add_pipeline(intseq, AbstractActor(plumbing.Buffer), dma_lasmi.Reader(lasmim), dma_out)

            cast = structuring.Cast(lasmim.dw, epixel_layout, reverse_to=True)
            g.add_connection(dma_out, cast)
            g.add_connection(cast, self.blender, sink_subr=["i"+str(n)])

        vtg = VTG(pack_factor)
        g.add_connection(self.fi, vtg, source_subr=self.fi.timing_subr, sink_ep="timing")
        g.add_connection(self.blender, vtg, sink_ep="pixels")
        g.add_connection(vtg, self.driver)
        self.submodules += CompositeActor(g)