def _resolve(self, expr): sim = Simulator(Module()) a = [] def testbench(): a.append((yield expr)) sim.add_process(testbench) sim.run() return a[0]
def testbench(): from nmigen.sim.pysim import Settle, Simulator unit = NotGate() def bench(): yield unit.input.eq(0) yield Settle() assert (yield unit.output) yield unit.input.eq(1) yield Settle() assert not (yield unit.output) sim = Simulator(unit) sim.add_process(bench) with sim.write_vcd("notgate.vcd", "notgate.gtkw", traces=[unit.input, unit.output]): sim.run()