def elaborate(self, platform):
m = Module()
m.submodules += [
self.timing,
self.still,
]
return m
if __name__ == '__main__':
color_depth = 4
image = gradient(color_depth=color_depth)
timing = VgaTiming(resolutions[ResolutionName.VGA_640_480p_60hz])
dut = TestBench(
timing,
Still(timing, color_depth=color_depth, image=image),
)
sim = Simulator(dut)
def proc():
for _ in range(800 * 40):
yield
sim.add_clock(1e-6, domain='pixel')
sim.add_sync_process(proc, domain='pixel')
with sim.write_vcd('still.vcd'):
sim.run()
"""
from nmigen import Signal, Elaboratable, Module
from nmigen.sim.pysim import Simulator
class Top(Elaboratable):
def __init__(self):
self.counter = Signal(range(10))
def elaborate(self, platform):
m = Module()
m.d.sync += self.counter.eq(self.counter + 1)
return m
if __name__ == '__main__':
def process():
for tick in range(10):
print(f"counter = {(yield dut.counter)}")
yield
dut = Top()
sim = Simulator(dut)
sim.add_clock(1e-6)
sim.add_sync_process(process)
with sim.write_vcd(f"{__file__[:-3]}.vcd"):
sim.run()
m.d.comb += dllpt.send.eq(1)
sim = Simulator(m)
sim.add_clock(1 / 125e6, domain="rx")
# The other two DLLPs received from the ROCKPro64
# Refer to layouts.py for the layout of the dllp record
dllp_1 = 0b1000011100000001000000000100
dllp_2 = 0b1000000100000001000000000101
def process():
yield dllpt.dllp.eq(dllp_1)
#yield dllpt.dllp.valid.eq(0)
for _ in range(20):
print(hex((yield dllpt.source.symbol[0])), end="\t")
print(hex((yield dllpt.source.symbol[1])), end="\t")
print(hex((yield dllpt.source.symbol[2])), end="\t")
print(hex((yield dllpt.source.symbol[3])))
print(hex((yield dllpt.dllp)))
print(hex((yield dllpt.dllp.valid)))
print(hex((yield dllpt.dllp_data)))
#print(hex((yield dllpt.symbols[0])), end="\t")
#print(hex((yield dllpt.symbols[1])))
#print(hex((yield dllpt.crc_out)))
print()
yield
sim.add_sync_process(process, domain="rx")
with sim.write_vcd("test.vcd", "test.gtkw"):
sim.run()
def test_sim_noiseshaper(self):
fmt = Q(8, 18)
input = fmt.Signal()
dut = Noiseshaper(input, order=8, n_lev=64)
sim = Simulator(dut)
sim.add_clock(1 / 100e6)
input_hist = []
output_hist = []
integrators_hist = [[] for _ in dut.stages]
n = 8192
f_nyquist = int(np.ceil(n / (2. * dut.osr)))
f_test = np.floor(2. / 3. * f_nyquist)
u = dut.n_lev * 0.5 * np.sin(2 * np.pi * f_test / n * np.arange(n))
def testbench():
for x in u:
yield input.eq(x)
input_hist.append(fmt.to_float((yield input.value)))
output_hist.append(
fmt.to_float((yield dut.quantized_value.value)))
for i, integrator in enumerate(dut.stages):
integrators_hist[i].append(
fmt.to_float((yield integrator.value)))
yield
sim.add_sync_process(testbench)
sim.run()
from matplotlib import pyplot as plt
plt.plot(np.arange(n), output_hist, linewidth=1, label="output")
plt.plot(np.arange(n), input_hist, label="input")
plt.legend()
plt.show()
for i, integrator_hist in reversed(list(enumerate(integrators_hist))):
plt.plot(np.arange(n),
integrator_hist,
linewidth=1,
label="integrator {}".format(i))
plt.legend()
plt.show()
import deltasigma as ds
f = np.linspace(0, 0.5, int(n / 2. + 1))
v, xn, xmax, y = ds.simulateDSM(u,
dut.h,
nlev=len(dut.quantization_values))
spec = np.fft.fft(v * ds.ds_hann(n)) / (n / 4)
plt.plot(f, ds.dbv(spec[:int(n / 2. + 1)]), 'b', label='Simulation DS')
spec = np.fft.fft(output_hist * ds.ds_hann(n)) / (n / 4)
plt.plot(f,
ds.dbv(spec[:int(n / 2. + 1)]),
'g',
label='Simulation HW',
alpha=0.7)
ds.figureMagic([0, 0.5], 0.05, None, [-160, 0], 20, None, (16, 6),
'Output Spectrum')
plt.xlabel('Normalized Frequency')
plt.ylabel('dBFS')
snr = ds.calculateSNR(spec[2:f_nyquist + 1], f_test - 2)
plt.text(0.05,
-10,
'SNR = %4.1fdB @ OSR = %d' % (snr, dut.osr),
verticalalignment='center')
NBW = 1.5 / n
Sqq = 4 * ds.evalTF(dut.h, np.exp(2j * np.pi * f))**2 / 3.
plt.plot(f, ds.dbp(Sqq * NBW), 'm', linewidth=2, label='Expected PSD')
plt.text(0.49,
-90,
'NBW = %4.1E x $f_s$' % NBW,
horizontalalignment='right')
plt.legend(loc=4)
plt.show()
pwm_out = py_pwm.modulate(np.array(output_hist) + 32,
n_bits=6,
oversampling_ratio=1)
n = n * 64
f = np.linspace(0, 0.5, int(n / 2. + 1))
spec = np.fft.fft(pwm_out * ds.ds_hann(n)) / (n / 4)
plt.plot(f, ds.dbv(spec[:int(n / 2. + 1)]), 'b', label='PWM')
ds.figureMagic([0, 0.5], 0.05, None, [-160, 0], 20, None, (16, 6),
'Output Spectrum')
plt.xlabel('Normalized Frequency')
plt.ylabel('dBFS')
snr = ds.calculateSNR(spec[2:f_nyquist + 1], f_test - 2)
plt.text(0.05,
-10,
'SNR = %4.1fdB @ OSR = %d' % (snr, dut.osr),
verticalalignment='center')
plt.legend(loc=4)
plt.show()