def handle_exception(s, instr, packet):
s.CSR[CsrRegisters.mtval] = instr
s.CSR[CsrRegisters.mcause] = packet.mcause
s.CSR[CsrRegisters.mepc] = s.PC
mtvec = s.CSR[CsrRegisters.mtvec]
mode = mtvec[0:2]
base = concat(mtvec[2:XLEN], Bits(2, 0))
if mode == MtvecMode.direct:
target = base
elif mode == MtvecMode.vectored:
target = base + (packet.mcause << 2)
else:
# this is a bad state. mtvec is curcial to handling
# exceptions, and there is no way to handle and exception
# related to mtvec.
# In a real processor, this would probably just halt or reset
# the entire processor
assert False
s.PC = target
def execute_jal( s, inst ): s.R[31] = s.PC + 4 s.PC = concat( (s.PC+4)[28:32], inst.jtarg, Bits(2,0) )
def execute_j( s, inst ): s.PC = concat( (s.PC+4)[28:32], inst.jtarg, Bits(2,0) )
def u_imm(self):
return concat(self.bits[tinyrv2_field_slice_u_imm], Bits(12, 0))
def augment_u_imm(s, u_imm):
return concat(u_imm, Bits(12, 0))
def execute_jal(s, inst):
s.R[31] = s.PC + 4
s.PC = concat((s.PC + 4)[28:32], inst.jtarg, Bits(2, 0))
def execute_j(s, inst):
s.PC = concat((s.PC + 4)[28:32], inst.jtarg, Bits(2, 0))
