def test_pymtl3_list_interface_views(): a = CaseBits32MsgRdyIfcOnly.DUT() a.elaborate() assert rt.is_rtlir_convertible(a.in_) assert rt.get_rtlir( a.in_ ) == \ rt.Array([5], rt.InterfaceView('Bits32MsgRdyIfc', {'msg':rt.Port('output', rdt.Vector(32)), 'rdy':rt.Port('input', rdt.Vector(1))}))
def test_pymtl_list_components(): a = CaseBits32InOutx5CompOnly.DUT() a.elaborate() assert rt.is_rtlir_convertible(a.b) assert rt.get_rtlir( a.b ) == \ rt.Array([5], rt.Component( a.b[0], { 'clk':rt.Port('input', rdt.Vector(1)), 'reset':rt.Port('input', rdt.Vector(1)), 'in_':rt.Port('input', rdt.Vector(32)), 'out':rt.Port('output', rdt.Vector(32)), }))
def visit_Attribute(s, node): if isinstance(node.value.Type, rt.Signal): dtype = node.value.Type.get_dtype() if not isinstance(dtype, rdt.Struct): raise PyMTLTypeError( s.blk, node.ast, 'attribute base should be a struct signal!') if not dtype.has_property(node.attr): raise PyMTLTypeError( s.blk, node.ast, f'{dtype.get_name()} does not have field {node.attr}!') dtype = dtype.get_property(node.attr) if isinstance(node.value.Type, rt.Port): rtype = rt.Port(node.value.Type.get_direction(), dtype) elif isinstance(node.value.Type, rt.Wire): rtype = rt.Wire(dtype) elif isinstance(node.value.Type, rt.Const): obj = node.value.Type.get_object() if obj is None: rtype = rt.Const(dtype) else: try: rtype = rt.Const(dtype, getattr(obj, node.attr)) except AttributeError: rtype = rt.Const(dtype) else: raise PyMTLTypeError( s.blk, node.ast, f'unrecognized signal type {node.value.Type}!') node.Type = rtype else: super().visit_Attribute(node)
def test_pymtl_list_components(): class B(dsl.Component): def construct(s): s.in_ = dsl.InPort(Bits32) s.out = dsl.OutPort(Bits32) class A(dsl.Component): def construct(s): s.b = [B() for _ in range(5)] a = A() a.elaborate() assert rt.is_rtlir_convertible(a.b) assert rt.Array([5], rt.Component( a.b[0], {'in_':rt.Port('input', rdt.Vector(32)), 'out':rt.Port('output', rdt.Vector(32))})) == \ rt.get_rtlir( a.b )
def test_pymtl3_list_interface_views(): class Ifc(dsl.Interface): def construct(s): s.msg = dsl.OutPort(Bits32) s.rdy = dsl.InPort(Bits1) class A(dsl.Component): def construct(s): s.in_ = [Ifc() for _ in range(5)] a = A() a.elaborate() assert rt.is_rtlir_convertible(a.in_) assert rt.Array([5], rt.InterfaceView('Ifc', {'msg':rt.Port('output', rdt.Vector(32)), 'rdy':rt.Port('input', rdt.Vector(1))})) == \ rt.get_rtlir( a.in_ )
def test_pymtl_struct_closure(do_test): a = CaseStructClosureGlobal.DUT() a.elaborate() a._rtlir_freevar_ref = { 'foo_at_upblk': (a._foo, rt.Port("input", rdt.Struct("Bits32Foo", {"foo": rdt.Vector(32)}))) } do_test(a)
def __init__(s, index_base, index): base_rtype = index_base.get_rtype() dtype = base_rtype.get_dtype() if isinstance(base_rtype, rt.Port): rtype = rt.Port(base_rtype.get_direction(), rdt.Vector(1)) elif isinstance(base_rtype, rt.Wire): rtype = rt.Wire(rdt.Vector(1)) else: assert False, f"unrecognized signal type {base_rtype} for indexing" super().__init__(index_base, index, rtype)
def __init__( s, attr_base, attr ): base_rtype = attr_base.get_rtype() dtype = base_rtype.get_dtype() if isinstance( base_rtype, rt.Port ): rtype = rt.Port( base_rtype.get_direction(), dtype.get_property( attr ) ) elif isinstance( base_rtype, rt.Wire ): rtype = rt.Wire( dtype.get_property( attr ) ) else: assert False, f"unrecognized signal type {base_rtype} for field selection" super().__init__( attr_base, attr, rtype )
def test_pymtl3_list_ports(): class A(dsl.Component): def construct(s): s.in_ = [dsl.InPort(Bits32) for _ in range(5)] a = A() a.elaborate() assert rt.is_rtlir_convertible(a.in_) assert rt.Array([5], rt.Port('input', rdt.Vector(32))) == rt.get_rtlir(a.in_)
def test_pymtl_list_multi_dimension(): class A(dsl.Component): def construct(s): s.out = [[[dsl.OutPort(Bits32) for _ in range(1)] \ for _ in range(2)] for _ in range(3)] a = A() a.elaborate() assert rt.is_rtlir_convertible(a.out) assert rt.Array([3, 2, 1], rt.Port('output', rdt.Vector(32))) == rt.get_rtlir(a.out)
def __init__( s, slice_base, start, stop ): base_rtype = slice_base.get_rtype() dtype = base_rtype.get_dtype() if isinstance( base_rtype, rt.Port ): rtype = rt.Port( base_rtype.get_direction(), rdt.Vector( stop-start ) ) elif isinstance( base_rtype, rt.Wire ): rtype = rt.Wire( rdt.Vector( stop-start ) ) else: assert False, f"unrecognized signal type {base_rtype} for slicing" super().__init__( rtype ) s.base = slice_base s.slice = ( start, stop )
def __init__(s, index_base, index): base_rtype = index_base.get_rtype() dtype = base_rtype.get_dtype() if isinstance(base_rtype, rt.Port): rtype = rt.Port(base_rtype.get_direction(), dtype.get_next_dim_type()) elif isinstance(base_rtype, rt.Wire): rtype = rt.Wire(dtype.get_next_dim_type()) else: assert False, \ "unrecognized signal type {} for indexing".format( base_rtype ) super().__init__(index_base, index, rtype)
def test_pymtl3_interface_wire(): a = CaseBits32WireIfcOnly.DUT() a.elaborate() # in_.foo will be silently dropped! assert rt.get_rtlir(a.in_) == rt.InterfaceView( 'Bits32FooWireBarInIfc', {'bar': rt.Port('input', rdt.Vector(32))})
def test_pymtl_list_multi_dimension(): a = CaseBits32Outx3x2x1PortOnly.DUT() a.elaborate() assert rt.is_rtlir_convertible(a.out) assert rt.get_rtlir(a.out) == rt.Array([3, 2, 1], rt.Port('output', rdt.Vector(32)))
def test_pymtl3_list_ports(): a = CaseBits32x5PortOnly.DUT() a.elaborate() assert rt.is_rtlir_convertible(a.in_) assert rt.get_rtlir(a.in_) == rt.Array([5], rt.Port('input', rdt.Vector(32)))