def __init__(s, translation_top): s.tr_top = translation_top if not hasattr(translation_top, "_rtlir_getter"): translation_top._rtlir_getter = rt.RTLIRGetter(cache=True)
def test_pymtl3_list_consts(): a = CaseBits32x5ConstOnly.DUT() a.elaborate() getter = rt.RTLIRGetter() assert rt.is_rtlir_convertible( a.in_ ) assert rtlir_getter.get_rtlir( a.in_ ) == rt.Array([5], rt.Const(rdt.Vector(32)))
def __init__(s, translation_top): c = s.__class__ s.tr_top = translation_top if not translation_top.has_metadata(c.rtlir_getter): translation_top.set_metadata(c.rtlir_getter, rt.RTLIRGetter(cache=True))
from pymtl3 import Bits16 from pymtl3.passes.rtlir.errors import RTLIRConversionError from pymtl3.passes.rtlir.rtype import RTLIRDataType as rdt from pymtl3.passes.rtlir.rtype import RTLIRType as rt from pymtl3.passes.rtlir.util.test_utility import expected_failure from pymtl3.passes.testcases import ( CaseBits32InOutx5CompOnly, CaseBits32MsgRdyIfcOnly, CaseBits32Outx3x2x1PortOnly, CaseBits32WireIfcOnly, CaseBits32x5ConstOnly, CaseBits32x5PortOnly, CaseBits32x5WireOnly, ) rtlir_getter = rt.RTLIRGetter() def test_pymtl3_list_ports(): a = CaseBits32x5PortOnly.DUT() a.elaborate() assert rt.is_rtlir_convertible( a.in_ ) assert rtlir_getter.get_rtlir( a.in_ ) == rt.Array([5], rt.Port('input', rdt.Vector(32))) def test_pymtl3_list_wires(): a = CaseBits32x5WireOnly.DUT() a.elaborate() assert rt.is_rtlir_convertible( a.in_ ) assert rtlir_getter.get_rtlir( a.in_ ) == rt.Array([5], rt.Wire(rdt.Vector(32))) def test_pymtl3_list_consts(): a = CaseBits32x5ConstOnly.DUT()