def visit_Attribute(s, node):
"""Return the SystemVerilog representation of an attribute.
Add support for accessing struct attribute in L3.
"""
if isinstance(node.value.Type, rt.Signal):
if isinstance(node.value.Type, rt.Const):
try:
obj = node.Type.get_object()
except AttributeError:
obj = None
if obj is None:
raise SVerilogTranslationError( s.blk, node,
"attribute ({}) of constant struct instance ({}) is not supported!". \
format( node.attr, node.value ) )
else:
if isinstance(obj, Bits):
s.signal_expr_prologue(node)
node.sexpr['s_attr'] = \
s._literal_number(obj.nbits, int(obj.value))
node.sexpr["s_index"] = ""
attr = node.attr
return s.signal_expr_epilogue(
node, "{attr}".format(**locals()))
elif isinstance(obj, BitStruct):
s.signal_expr_prologue(node)
node.sexpr['s_attr'] = \
s._struct_instance(node.Type.get_dtype(), obj)
node.sexpr["s_index"] = ""
attr = node.attr
return s.signal_expr_epilogue(
node, "{attr}".format(**locals()))
else:
raise SVerilogTranslationError( s.blk, node,
"attribute ({}) of constant struct instance ({}) is not supported!". \
format( node.attr, node.value ) )
elif isinstance(node.value.Type.get_dtype(), rdt.Struct):
value = s.visit(node.value)
s.signal_expr_prologue(node)
attr = node.attr
s.check_res(node, attr)
node.sexpr['s_attr'] += "__{}"
node.sexpr['attr'].append(attr)
return s.signal_expr_epilogue(
node, "{value}.{attr}".format(**locals()))
return super().visit_Attribute(node)
def visit_Index(s, node):
node.idx._top_expr = 1
idx = s.visit(node.idx)
value = s.visit(node.value)
Type = node.value.Type
s.signal_expr_prologue(node)
# Unpacked index
if isinstance(Type, rt.Array):
subtype = Type.get_sub_type()
if isinstance(subtype, rt.Const):
nbits = subtype.get_dtype().get_length()
try:
const_value = node._value
except AttributeError:
raise SVerilogTranslationError(
s.blk, node,
"{} is not an array of constants!".format(value))
node.sexpr['s_index'] = "{nbits}'d{const_value}".format(
**locals())
node.sexpr['index'] = []
node.sexpr['s_attr'] = ""
node.sexpr['attr'] = []
else:
node.sexpr['s_index'] += '[{}]'
node.sexpr['index'].append(idx)
# Index on a signal
elif isinstance(Type, rt.Signal):
# Packed index or bit selection
if Type.is_packed_indexable() or isinstance(
Type.get_dtype(), rdt.Vector):
node.sexpr['s_index'] += '[{}]'
node.sexpr['index'].append(idx)
else:
raise SVerilogTranslationError(
s.blk, node, "internal error: unrecognized index")
else:
raise SVerilogTranslationError(
s.blk, node, "internal error: unrecognized index")
return s.signal_expr_epilogue(node, value + '[{}]'.format(idx))
def visit_FreeVar(s, node):
if isinstance(node.obj, int):
return f"32'd{node.obj}"
elif isinstance(node.obj, Bits):
nbits = node.obj.nbits
value = int(node.obj)
return f"{nbits}'d{value}"
else:
raise SVerilogTranslationError(
s.blk, node, f"{node.name} {node.obj} is not an integer!")
def visit_Reduce(s, node):
op_t = type(node.op)
reduce_ops = {bir.BitAnd: '&', bir.BitOr: '|', bir.BitXor: '^'}
if op_t not in reduce_ops:
raise SVerilogTranslationError(
s.blk, node,
"unrecognized operator {} for reduce method!".format(op_t))
value = s.visit(node.value)
op = reduce_ops[op_t]
return "( {op} {value} )".format(**locals())
def visit_FreeVar(s, node):
if isinstance(node.obj, int):
return "32'd{}".format(node.obj)
elif isinstance(node.obj, Bits):
nbits = node.obj.nbits
value = int(node.obj.value)
return "{nbits}'d{value}".format(**locals())
else:
raise SVerilogTranslationError(
s.blk, node,
"{} {} is not an integer!".format(node.name, node.obj))
def visit_ZeroExt(s, node):
value = s.visit(node.value)
try:
target_nbits = int(node.nbits._value)
except AttributeError:
raise SVerilogTranslationError(
s.blk, node,
"new bitwidth of zero extension must be known at elaboration time!"
)
current_nbits = int(node.value.Type.get_dtype().get_length())
padded_nbits = target_nbits - current_nbits
return f"{{ {{ {padded_nbits} {{ 1'b0 }} }}, {value} }}"
def visit_Attribute(s, node):
s.signal_expr_prologue(node)
Type = node.Type
if isinstance(Type, rt.Const):
obj = Type.get_object()
if isinstance(obj, int):
node.sexpr['s_attr'] = "32'd{}".format(obj)
node.sexpr['s_index'] = ""
elif isinstance(obj, Bits):
nbits = obj.nbits
value = int(obj.value)
node.sexpr['s_attr'] = "{nbits}'d{value}".format(**locals())
node.sexpr['s_index'] = ""
elif isinstance(obj, BitStruct):
node.sexpr['s_attr'] = s._struct_instance(
node.Type.get_dtype(), obj)
node.sexpr['s_index'] = ""
else:
raise SVerilogTranslationError(
s.blk, node,
"{} {} is not an integer!".format(node.attr, obj))
elif isinstance(node.value, bir.Base):
# The base of this attribute node is the component 's'.
# Example: s.out, s.STATE_IDLE
# assert node.value.base is s.component
s.check_res(node, node.attr)
node.sexpr['s_attr'] = "{}"
node.sexpr['attr'].append(node.attr)
else:
raise SVerilogTranslationError(
s.blk, node, "sub-components are not supported at L1")
return s.signal_expr_epilogue(node, node.attr)
def visit_Index( s, node ):
if isinstance( node.value.Type, rt.Array ) and \
isinstance( node.value.Type.get_sub_type(), rt.Component ):
try:
idx = node.idx._value
except AttributeError:
raise SVerilogTranslationError( s.blk, node,
'index of component array must be a static constant expression!' )
idx = int( idx )
value = s.visit( node.value )
return f"{value}__{idx}"
else:
return super().visit_Index( node )
def visit_Index(s, node):
idx = s.visit(node.idx)
value = s.visit(node.value)
Type = node.value.Type
# Unpacked index
if isinstance(Type, rt.Array):
subtype = Type.get_sub_type()
# Unpacked array index must be a static constant integer!
# if idx is None and not isinstance(subtype, (rt.Port, rt.Wire, rt.Const)):
# raise SVerilogTranslationError( s.blk, node.ast,
# 'index of unpacked array {} must be a constant integer expression!'. \
# format(node.value) )
if isinstance(subtype, (rt.Port, rt.Wire, rt.Const)):
return '{value}[{idx}]'.format(**locals())
else:
return '{value}__{idx}'.format(**locals())
# Index on a signal
elif isinstance(Type, rt.Signal):
# Packed index
if Type.is_packed_indexable():
return '{value}[{idx}]'.format(**locals())
# Bit selection
elif isinstance(Type.get_dtype(), rdt.Vector):
return '{value}[{idx}]'.format(**locals())
else:
raise SVerilogTranslationError(
s.blk, node, "internal error: unrecognized index")
else:
raise SVerilogTranslationError(
s.blk, node, "internal error: unrecognized index")
def visit_Index(s, node):
if isinstance( node.value.Type, rt.Array ) and \
isinstance( node.value.Type.get_sub_type(), rt.InterfaceView ):
try:
nbits = node.idx._value
except AttributeError:
raise SVerilogTranslationError( s.blk, node,
'index of interface array {} must be a static constant expression!'. \
format( node.idx ) )
idx = int(nbits)
value = s.visit(node.value)
return "{value}__{idx}".format(**locals())
else:
return super().visit_Index(node)
def visit_SignExt(s, node):
value = s.visit(node.value)
try:
target_nbits = int(node.nbits._value)
except AttributeError:
raise SVerilogTranslationError(
s.blk, node,
"new bitwidth of sign extension must be known at elaboration time!"
)
current_nbits = int(node.value.Type.get_dtype().get_length())
last_bit = current_nbits - 1
padded_nbits = target_nbits - current_nbits
template = "{{ {{ {padded_nbits} {{ {value}[{last_bit}] }} }}, {value} }}"
one_bit_template = "{{ {{ {padded_nbits} {{ {_value} }} }}, {value} }}"
# Check if the signal to be extended is a bit selection or one-bit part
# selection.
if isinstance(node.value, bir.Slice):
try:
lower = node.value.lower._value
upper = node.value.upper._value
if upper - lower == 1:
_one_bit = True
else:
_one_bit = False
except AttributeError:
_one_bit = False
# Manipulate the slicing string to avoid indexing on a sliced signal
if not _one_bit:
l, col, r = value.rfind('['), value.rfind(':'), value.rfind(
']')
if -1 < l < col < r:
_value = value[:col] + ']'
return one_bit_template.format(**locals())
elif isinstance(node.value, bir.Index):
_one_bit = True
else:
_one_bit = False
if _one_bit:
_value = value
return one_bit_template.format(**locals())
else:
return template.format(**locals())
def visit_Attribute(s, node):
attr = node.attr
value = s.visit(node.value)
s.check_res(node, attr)
if isinstance(node.value, bir.Base):
# The base of this attribute node is the component 's'.
# Example: s.out, s.STATE_IDLE
# assert node.value.base is s.component
ret = attr
else:
raise SVerilogTranslationError(
s.blk, node, "sub-components are not supported at L1")
return ret
def visit_IfExp(s, node):
raise SVerilogTranslationError(s.blk, node,
"IfExp not supported at L1")
def visit_LoopVarDecl(s, node):
raise SVerilogTranslationError(s.blk, node,
"LoopVarDecl not supported at L1")
def visit_TmpVar(s, node):
raise SVerilogTranslationError(s.blk, node,
"TmpVar not supported at L1")
def visit_Compare(s, node):
raise SVerilogTranslationError(s.blk, node,
"Compare not supported at L1")
def visit_BinOp(s, node):
raise SVerilogTranslationError(s.blk, node,
"BinOp not supported at L1")
def visit_StructInst(s, node):
raise SVerilogTranslationError(s.blk, node,
"StructInst not supported at L1")
def check_res(s, node, name):
if s.is_sverilog_reserved(name):
raise SVerilogTranslationError(
s.blk, node,
"name {} is a SystemVerilog reserved keyword!".format(name))