Esempio n. 1
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    def ld8(cpu, opcode, logger):
        regIndPrim = (opcode & 7)
        regInd = (opcode >> 3) & 7
        cpu.regs[regInd] = cpu.regs[regIndPrim]

        cpu.m_cycles, cpu.t_states = 1, 4
        logger.info("LD {}, {}".format(
            IndexToReg.translate8Bit(regInd),
            IndexToReg.translate8Bit(regIndPrim)))
Esempio n. 2
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    def inc16(cpu, opcode, logger):

        regInd = (opcode & 0x30) >> 4
        cpu.Reg16(regInd, cpu.Reg16(regInd) + 1)

        cpu.m_cycles, cpu.t_states = 1, 6
        logger.info("INC {0}".format(IndexToReg.translate16Bit(regInd)))
Esempio n. 3
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    def ld_r_iy_d(cpu, opcode, logger):
        index = (opcode >> 3) & 7
        d = cpu.ram[cpu.PC]
        cpu.regs[index] = cpu.ram[cpu.IY + d]

        cpu.m_cycles, cpu.t_states = 5, 19
        logger.info("LD {}, (IY+{:02X})".format(IndexToReg.translate8Bit(index), d))
Esempio n. 4
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    def dec16b(cpu, opcode, logger):
        regInd = (opcode >> 4) & 3

        cpu.Reg16(regInd, cpu.Reg16(regInd) - 1)

        cpu.m_cycles, cpu.t_states = 1, 6
        logger.info("DEC {}".format(IndexToReg.translate16Bit(regInd)))
Esempio n. 5
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    def ld8n(cpu, opcode, logger):
        regInd = (opcode >> 3) & 7
        value = cpu.ram[cpu.PC]
        cpu.regs[regInd] = value

        cpu.m_cycles, cpu.t_states = 2, 7
        logger.info("LD {}, {:02X}".format(
            IndexToReg.translate8Bit(regInd),
            value))
Esempio n. 6
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    def ld_r_hl(cpu, opcode, logger):
        index = (opcode >> 3) & 7

        value = cpu.ram[cpu.HL]

        cpu.regs[index] = value

        cpu.m_cycles, cpu.t_states = 2, 7
        logger.info("LD {}, (HL)".format(IndexToReg.translate8Bit(index)))
Esempio n. 7
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    def push(cpu, opcode, logger):
        regInd = (opcode >> 4) & 3
        value = cpu.Reg16(regInd, af=True)

        cpu.ram[cpu.SP-1] = value >> 8
        cpu.ram[cpu.SP-2] = value & 255
        cpu.SP -= 2
        cpu.m_cycles, cpu.t_states = 3, 11
        logger.info("PUSH {}".format(IndexToReg.translate16Bit(regInd)))
Esempio n. 8
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    def pop(cpu, opcode, logger):
        regInd = (opcode >> 4) & 3
        high = cpu.ram[cpu.SP+1]
        low = cpu.ram[cpu.SP]
        cpu.SP += 2
        val = (high << 8) + low

        cpu.Reg16(regInd, val, af=True)

        cpu.m_cycles, cpu.t_states = 3, 7
        logger.info("POP {}".format(IndexToReg.translate16Bit(regInd)))
Esempio n. 9
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 def cp(cpu, opcode, logger):
     regInd = opcode & 7
     value = cpu.A - cpu.regs[regInd]
     cpu.ZFlag = Bits.isZero(value)
     cpu.CFlag = Bits.carryFlag(value)
     cpu.NFlag = Bits.set()
     cpu.HFlag = Bits.halfCarrySub(cpu.A, value)
     cpu.SFlag = Bits.signFlag(value)
     cpu.PVFlag = Bits.overflow(value, cpu.A)
     cpu.m_cycles, cpu.t_states = 1, 4
     logger.info("CP {}".format(IndexToReg.translate8Bit(regInd)))
Esempio n. 10
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    def add_iy_rr(cpu, opcode, logger):
        regInd = (opcode >> 4) & 3
        val = cpu.Reg16(regInd, iy=True)

        old = cpu.IY
        cpu.IY = cpu.IY + val
        cpu.NFlag = Bits.reset()
        cpu.HFlag = Bits.carryFlagAdd16(old, cpu.IY)
        cpu.CFlag = Bits.overflow(old, cpu.IY, bits=16)
        cpu.m_cycles, cpu.t_states = 4, 15
        logger.info("ADD IY, {}".format(IndexToReg.translate16Bit(regInd)))
Esempio n. 11
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    def adc_r(cpu, opcode, logger):
        reg_idx = (opcode & 7)
        old_val = cpu.A
        cpu.A = old_val + cpu.regs[reg_idx] + (1 if cpu.CFlag else 0)

        cpu.SFlag = Bits.isNegative(cpu.A)
        cpu.ZFlag = Bits.isZero(cpu.A)
        cpu.NFlag = Bits.reset()

        cpu.m_cycles, cpu.t_states = 1, 4
        logger.info("ADC A, {}".format(IndexToReg.translate8Bit(reg_idx)))
Esempio n. 12
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    def ld16(cpu, opcode, logger):
        regInd = (opcode & 0x30) >> 4
        loValue = cpu.ram[cpu.PC]
        hiValue = cpu.ram[cpu.PC]
        value = (hiValue << 8) + loValue

        cpu.Reg16(regInd, value)

        cpu.m_cycles, cpu.t_states = 2, 10
        logger.info("LD {}, {:04X}".format(
            IndexToReg.translate16Bit(regInd),
            value))
Esempio n. 13
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    def add16(cpu, opcode, logger):
        regInd = (opcode & 0x30) >> 4
        value = cpu.Reg16(regInd)

        oldHL = cpu.HL
        cpu.HL = cpu.HL + value

        cpu.NFlag = Bits.reset()
        cpu.CFlag = Bits.carryFlag16(oldHL, cpu.HL)
        cpu.HFlag = Bits.carryFlag16(oldHL, cpu.HL, bits=11)
        cpu.m_cycles, cpu.t_states = 3, 11
        logger.info("ADD HL, {}".format(IndexToReg.translate16Bit(regInd)))
Esempio n. 14
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    def ldNnRr(cpu, opcode, logger):
        regInd = (opcode & 0x30) >> 4
        high = cpu.ram[cpu.PC]
        low = cpu.ram[cpu.PC]
        addr = (high << 8) + low

        value = cpu.Reg16(regInd)

        cpu.ram[addr + 1] = value >> 8
        cpu.ram[addr] = value & 0xFF
        cpu.m_cycles, cpu.t_states = 6, 20
        logger.info("LD ({:04X}), {}".format(addr, IndexToReg.translate16Bit(regInd)))
Esempio n. 15
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	def inc16(cpu, opcode, logger):
		
		regInd = (opcode & 0x30) >> 4
		logger.info("INC {0}".format(IndexToReg.translate16bit(regInd)))
		if regInd == 0:
			cpu.BC = cpu.BC + 1
		elif regInd == 1:
			cpu.DE = cpu.DE + 1
		elif regInd == 2:
			cpu.HL = cpu.HL + 1
		elif regInd == 3:
			cpu.SP = cpu.SP + 1
Esempio n. 16
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    def _or(cpu, opcode, logger):
        regInd = opcode & 7
        cpu.A = cpu.A | cpu.regs[regInd]
        cpu.HFlag = Bits.reset()
        cpu.CFlag = Bits.reset()
        cpu.NFlag = Bits.reset()
        cpu.ZFlag = Bits.isZero(cpu.A)
        cpu.SFlag = Bits.isNegative(cpu.A)
        cpu.PVFlag = Bits.isEvenParity(cpu.A)

        cpu.m_cycles, cpu.t_states = 1, 4
        logger.info("OR {}".format(IndexToReg.translate8Bit(regInd)))
Esempio n. 17
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    def ld16_nn(cpu, opcode, logger):
        low = cpu.ram[cpu.PC]
        high = cpu.ram[cpu.PC]
        addr = (high << 8) + low
        value_low = cpu.ram[addr]
        value_high = cpu.ram[addr+1]
        value = (value_high << 8) + value_low
        regInd = (opcode >> 4) & 3

        cpu.Reg16(regInd, value)

        cpu.m_cycles, cpu.t_states = 6, 20
        logger.info("LD {},({:0X})".format(IndexToReg.translate16Bit(regInd), addr))
Esempio n. 18
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    def inc8(cpu, opcode, logger):
        index = (opcode >> 3) & 7
        oldValue = cpu.regs[index]
        cpu.regs[index] = Bits.limitTo8Bits(cpu.regs[index] + 1)

        cpu.NFlag = Bits.reset()
        cpu.ZFlag = Bits.isZero(cpu.regs[index])
        cpu.HFlag = Bits.halfCarrySub(oldValue, cpu.regs[index])
        cpu.PVFlag = True if oldValue == 0x7f else False
        cpu.SFlag = Bits.isNegative(cpu.regs[index])

        cpu.m_cycles, cpu.t_states = 1, 4
        logger.info("INC {}".format(IndexToReg.translate8Bit(index)))
Esempio n. 19
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    def dec8b(cpu, opcode, logger):
        reg_index = (opcode >> 3) & 7
        old_val = cpu.regs[reg_index]
        cpu.regs[reg_index] = cpu.regs[reg_index] - 1

        cpu.ZFlag = Bits.isZero(cpu.regs[reg_index])
        cpu.SFlag = Bits.isNegative(cpu.regs[reg_index])
        cpu.NFlag = Bits.set()
        cpu.PVFlag = Bits.halfCarrySub(old_val, cpu.regs[reg_index])
        cpu.HFlag = Bits.halfCarrySub(old_val, cpu.regs[reg_index])

        cpu.m_cycles, cpu.t_states = 1, 4
        logger.info("DEC {}".format(IndexToReg.translate8Bit(reg_index)))
Esempio n. 20
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    def add_r(cpu, opcode, logger):
        index = (opcode & 7)
        old = cpu.A
        cpu.A = old + cpu.regs[index]

        cpu.SFlag = Bits.isNegative(cpu.A)
        cpu.ZFlag = Bits.isZero(cpu.A)
        cpu.HFlag = Bits.halfCarrySub(old, cpu.A)
        cpu.PVFlag = Bits.overflow(old, cpu.A)
        cpu.NFlag = Bits.reset()
        cpu.CFlag = Bits.carryFlag(cpu.A)

        cpu.m_cycles, cpu.t_states = 1, 4
        logger.info("ADD A, {}".format(IndexToReg.translate8Bit(index)))
Esempio n. 21
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    def sbc_r(cpu, opcode, logger):
        reg_idx = (opcode & 7)
        old_val = cpu.A
        cpu.A = old_val - cpu.regs[reg_idx] - (1 if cpu.CFlag else 0)

        cpu.SFlag = Bits.isNegative(cpu.A)
        cpu.ZFlag = Bits.isZero(cpu.A)
        cpu.NFlag = Bits.set()
        cpu.HFlag = Bits.halfCarrySub(old_val, cpu.A)
        cpu.PVFlag = Bits.overflow(old_val, cpu.A)
        cpu.CFlag = Bits.carryFlag(cpu.A)

        cpu.m_cycles, cpu.t_states = 1, 4
        logger.info("SDC A, {}".format(IndexToReg.translate8Bit(reg_idx)))
Esempio n. 22
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    def add_Hl_rr_c(cpu, opcode, logger):
        regInd = (opcode >> 4) & 3
        val = cpu.Reg16(regInd)

        old = cpu.HL
        cpu.HL = cpu.HL + val + (1 if cpu.CFlag else 0)
        cpu.SFlag = Bits.signFlag(cpu.HL, bits=16)
        cpu.ZFlag = Bits.isZero(cpu.HL)
        cpu.HFlag = Bits.halfCarrySub16(old, cpu.HL)
        cpu.PVFlag = Bits.overflow(old, cpu.HL, bits=16)
        cpu.NFlag = Bits.reset()
        cpu.CFlag = Bits.set() if (Bits.getNthBit(old, 15) == 1 and
                                   Bits.getNthBit(cpu.HL, 15) == 0) else Bits.reset()
        cpu.m_cycles, cpu.t_states = 4, 15
        logger.info("ADC HL, {}".format(IndexToReg.translate16Bit(regInd)))
Esempio n. 23
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    def srl_r(cpu, opcode, logger):
        reg_idx = (opcode & 7)
        old_val = cpu.regs[reg_idx]
        cpu.regs[reg_idx] = (old_val >> 1)
        last_bit = Bits.getNthBit(old_val, 0)

        cpu.CFlag = Bits.set() if last_bit == 1 else Bits.reset()
        cpu.NFlag = Bits.reset()
        cpu.HFlag = Bits.reset()
        cpu.ZFlag = Bits.isZero(cpu.regs[reg_idx])
        cpu.PVFlag = Bits.isEvenParity(cpu.regs[reg_idx])
        cpu.SFlag = Bits.reset()

        cpu.m_cycles, cpu.t_states = 2, 8
        logger.info("SRL {}".format(IndexToReg.translate8Bit(reg_idx)))
Esempio n. 24
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    def sub_r(cpu, opcode, logger):
        index = opcode & 7

        old_A = cpu.A
        cpu.A = cpu.A - cpu.regs[index]

        cpu.NFlag = Bits.set()
        cpu.SFlag = Bits.isNegative(cpu.A)
        cpu.ZFlag = Bits.isZero(cpu.A)
        cpu.HFlag = Bits.halfCarrySub(old_A, cpu.A)
        cpu.PVFlag = Bits.overflow(cpu.A, old_A)
        cpu.CFlag = Bits.carryFlag(cpu.A)

        cpu.m_cycles, cpu.t_states = 1, 4
        logger.info("SUB {}".format(IndexToReg.translate8Bit(index)))
Esempio n. 25
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	def ld16(cpu, opcode, logger):
		regInd = (opcode & 0x30) >> 4
		loValue = cpu.rom.readMemory(cpu.PC)
		hiValue = cpu.rom.readMemory(cpu.PC)
		value = (hiValue << 8) + loValue

		if regInd == 0:
			cpu.BC = value
		elif regInd == 1:
			cpu.DE = value
		elif regInd == 2:
			cpu.HL = value
		elif regInd == 3:
			cpu.SP = value

		logger.info("LD {0}, {1}".format(IndexToReg.translate16bit(regInd),value))
Esempio n. 26
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    def sbc(cpu, opcode, logger):
        regInd = (opcode & 0x30) >> 4
        value = cpu.Reg16(regInd)

        oldHL = cpu.HL

        cpu.HL = cpu.HL - value - (1 if cpu.CFlag else 0)

        cpu.SFlag = Bits.signFlag(cpu.HL, bits=16)
        cpu.ZFlag = Bits.isZero(cpu.HL)
        cpu.HFlag = Bits.halfCarrySub16(oldHL, cpu.HL)
        cpu.PVFlag = Bits.overflow(oldHL, cpu.HL, bits=16)
        cpu.NFlag = Bits.set()
        cpu.CFlag = Bits.borrow(cpu.HL, bits=16)

        cpu.m_cycles, cpu.t_states = 4, 15
        logger.info("SBC HL, {}".format(IndexToReg.translate16Bit(regInd)))
Esempio n. 27
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 def test_IndexToReg_translate8Bit_returns_A_for_7(self):
     self.assertEqual("A", IndexToReg.translate8Bit(7))
Esempio n. 28
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 def test_IndexToReg_translate16Bit_returns_BC_for_0(self):
     self.assertEqual("BC", IndexToReg.translate16Bit(0))
Esempio n. 29
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 def test_IndexToReg_translate16Bit_returns_DE_for_1(self):
     self.assertEqual("DE", IndexToReg.translate16Bit(1))
Esempio n. 30
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 def test_IndexToReg_translate16Bit_returns_HL_for_2(self):
     self.assertEqual("HL", IndexToReg.translate16Bit(2))
Esempio n. 31
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 def test_IndexToReg_translate8Bit_returns_E_for_3(self):
     self.assertEqual("E", IndexToReg.translate8Bit(3))
Esempio n. 32
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 def ldhlr(cpu, opcode, logger):
     regInd = opcode & 7
     cpu.ram[cpu.HL] = cpu.regs[regInd]
     cpu.m_cycles, cpu.t_states = 2, 7
     logger.info("LD (HL), {}".format(IndexToReg.translate8Bit(regInd)))
Esempio n. 33
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 def ldiy_d_r(cpu, opcode, logger):
     regInd = opcode & 7
     d = cpu.ram[cpu.PC]
     cpu.ram[cpu.IY + d] = cpu.regs[regInd]
     cpu.m_cycles, cpu.t_states = 5, 19
     logger.info("LD (IY+{:02X}), {}".format(d, IndexToReg.translate8Bit(regInd)))
Esempio n. 34
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 def test_IndexToReg_translate16Bit_returns_IY_for_2_and_iy_True(self):
     self.assertEqual("IY", IndexToReg.translate16Bit(2, iy=True))
Esempio n. 35
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 def test_IndextoReg_translate16Bit_returns_AF_for_3_and_af_True(self):
     self.assertEqual("AF", IndexToReg.translate16Bit(3, af=True))
Esempio n. 36
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 def test_IndexToReg_translate16Bit_returns_IY_for_2_and_iy_True(self):
     self.assertEquals("IY", IndexToReg.translate16Bit(2, iy=True))
Esempio n. 37
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 def test_IndextoReg_translate16Bit_returns_AF_for_3_and_af_True(self):
     self.assertEquals("AF", IndexToReg.translate16Bit(3, af=True))
Esempio n. 38
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 def test_IndexToReg_translate8Bit_returns_L_for_5(self):
     self.assertEqual("L", IndexToReg.translate8Bit(5))
Esempio n. 39
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 def test_IndexToReg_translate16Bit_returns_IX_for_2_and_ix_True(self):
     self.assertEqual("IX", IndexToReg.translate16Bit(2, ix=True))
Esempio n. 40
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 def test_IndexToReg_translate8Bit_returns_H_for_4(self):
     self.assertEqual("H", IndexToReg.translate8Bit(4))
Esempio n. 41
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 def test_IndexToReg_translate16Bit_returns_SP_for_3(self):
     self.assertEqual("SP", IndexToReg.translate16Bit(3))
Esempio n. 42
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 def test_IndexToReg_translate8Bit_returns_C_for_1(self):
     self.assertEqual("C", IndexToReg.translate8Bit(1))
Esempio n. 43
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 def test_IndexToReg_translate8Bit_returns_D_for_2(self):
     self.assertEqual("D", IndexToReg.translate8Bit(2))