def ld8(cpu, opcode, logger):
regIndPrim = (opcode & 7)
regInd = (opcode >> 3) & 7
cpu.regs[regInd] = cpu.regs[regIndPrim]
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("LD {}, {}".format(
IndexToReg.translate8Bit(regInd),
IndexToReg.translate8Bit(regIndPrim)))
def ld_r_iy_d(cpu, opcode, logger):
index = (opcode >> 3) & 7
d = cpu.ram[cpu.PC]
cpu.regs[index] = cpu.ram[cpu.IY + d]
cpu.m_cycles, cpu.t_states = 5, 19
logger.info("LD {}, (IY+{:02X})".format(IndexToReg.translate8Bit(index), d))
def ld8n(cpu, opcode, logger):
regInd = (opcode >> 3) & 7
value = cpu.ram[cpu.PC]
cpu.regs[regInd] = value
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("LD {}, {:02X}".format(
IndexToReg.translate8Bit(regInd),
value))
def ld_r_hl(cpu, opcode, logger):
index = (opcode >> 3) & 7
value = cpu.ram[cpu.HL]
cpu.regs[index] = value
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("LD {}, (HL)".format(IndexToReg.translate8Bit(index)))
def adc_r(cpu, opcode, logger):
reg_idx = (opcode & 7)
old_val = cpu.A
cpu.A = old_val + cpu.regs[reg_idx] + (1 if cpu.CFlag else 0)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.NFlag = Bits.reset()
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("ADC A, {}".format(IndexToReg.translate8Bit(reg_idx)))
def cp(cpu, opcode, logger):
regInd = opcode & 7
value = cpu.A - cpu.regs[regInd]
cpu.ZFlag = Bits.isZero(value)
cpu.CFlag = Bits.carryFlag(value)
cpu.NFlag = Bits.set()
cpu.HFlag = Bits.halfCarrySub(cpu.A, value)
cpu.SFlag = Bits.signFlag(value)
cpu.PVFlag = Bits.overflow(value, cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("CP {}".format(IndexToReg.translate8Bit(regInd)))
def _or(cpu, opcode, logger):
regInd = opcode & 7
cpu.A = cpu.A | cpu.regs[regInd]
cpu.HFlag = Bits.reset()
cpu.CFlag = Bits.reset()
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.PVFlag = Bits.isEvenParity(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("OR {}".format(IndexToReg.translate8Bit(regInd)))
def dec8b(cpu, opcode, logger):
reg_index = (opcode >> 3) & 7
old_val = cpu.regs[reg_index]
cpu.regs[reg_index] = cpu.regs[reg_index] - 1
cpu.ZFlag = Bits.isZero(cpu.regs[reg_index])
cpu.SFlag = Bits.isNegative(cpu.regs[reg_index])
cpu.NFlag = Bits.set()
cpu.PVFlag = Bits.halfCarrySub(old_val, cpu.regs[reg_index])
cpu.HFlag = Bits.halfCarrySub(old_val, cpu.regs[reg_index])
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("DEC {}".format(IndexToReg.translate8Bit(reg_index)))
def inc8(cpu, opcode, logger):
index = (opcode >> 3) & 7
oldValue = cpu.regs[index]
cpu.regs[index] = Bits.limitTo8Bits(cpu.regs[index] + 1)
cpu.NFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.regs[index])
cpu.HFlag = Bits.halfCarrySub(oldValue, cpu.regs[index])
cpu.PVFlag = True if oldValue == 0x7f else False
cpu.SFlag = Bits.isNegative(cpu.regs[index])
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("INC {}".format(IndexToReg.translate8Bit(index)))
def sbc_r(cpu, opcode, logger):
reg_idx = (opcode & 7)
old_val = cpu.A
cpu.A = old_val - cpu.regs[reg_idx] - (1 if cpu.CFlag else 0)
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.NFlag = Bits.set()
cpu.HFlag = Bits.halfCarrySub(old_val, cpu.A)
cpu.PVFlag = Bits.overflow(old_val, cpu.A)
cpu.CFlag = Bits.carryFlag(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("SDC A, {}".format(IndexToReg.translate8Bit(reg_idx)))
def add_r(cpu, opcode, logger):
index = (opcode & 7)
old = cpu.A
cpu.A = old + cpu.regs[index]
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.HFlag = Bits.halfCarrySub(old, cpu.A)
cpu.PVFlag = Bits.overflow(old, cpu.A)
cpu.NFlag = Bits.reset()
cpu.CFlag = Bits.carryFlag(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("ADD A, {}".format(IndexToReg.translate8Bit(index)))
def srl_r(cpu, opcode, logger):
reg_idx = (opcode & 7)
old_val = cpu.regs[reg_idx]
cpu.regs[reg_idx] = (old_val >> 1)
last_bit = Bits.getNthBit(old_val, 0)
cpu.CFlag = Bits.set() if last_bit == 1 else Bits.reset()
cpu.NFlag = Bits.reset()
cpu.HFlag = Bits.reset()
cpu.ZFlag = Bits.isZero(cpu.regs[reg_idx])
cpu.PVFlag = Bits.isEvenParity(cpu.regs[reg_idx])
cpu.SFlag = Bits.reset()
cpu.m_cycles, cpu.t_states = 2, 8
logger.info("SRL {}".format(IndexToReg.translate8Bit(reg_idx)))
def sub_r(cpu, opcode, logger):
index = opcode & 7
old_A = cpu.A
cpu.A = cpu.A - cpu.regs[index]
cpu.NFlag = Bits.set()
cpu.SFlag = Bits.isNegative(cpu.A)
cpu.ZFlag = Bits.isZero(cpu.A)
cpu.HFlag = Bits.halfCarrySub(old_A, cpu.A)
cpu.PVFlag = Bits.overflow(cpu.A, old_A)
cpu.CFlag = Bits.carryFlag(cpu.A)
cpu.m_cycles, cpu.t_states = 1, 4
logger.info("SUB {}".format(IndexToReg.translate8Bit(index)))
def test_IndexToReg_translate8Bit_returns_L_for_5(self):
self.assertEqual("L", IndexToReg.translate8Bit(5))
def test_IndexToReg_translate8Bit_returns_A_for_7(self):
self.assertEqual("A", IndexToReg.translate8Bit(7))
def ldhlr(cpu, opcode, logger):
regInd = opcode & 7
cpu.ram[cpu.HL] = cpu.regs[regInd]
cpu.m_cycles, cpu.t_states = 2, 7
logger.info("LD (HL), {}".format(IndexToReg.translate8Bit(regInd)))
def ldiy_d_r(cpu, opcode, logger):
regInd = opcode & 7
d = cpu.ram[cpu.PC]
cpu.ram[cpu.IY + d] = cpu.regs[regInd]
cpu.m_cycles, cpu.t_states = 5, 19
logger.info("LD (IY+{:02X}), {}".format(d, IndexToReg.translate8Bit(regInd)))
def test_IndexToReg_translate8Bit_returns_H_for_4(self):
self.assertEquals("H", IndexToReg.translate8Bit(4))
def test_IndexToReg_translate8Bit_returns_D_for_2(self):
self.assertEqual("D", IndexToReg.translate8Bit(2))
def test_IndexToReg_translate8Bit_returns_B_for_0(self):
self.assertEquals("B", IndexToReg.translate8Bit(0))
def test_IndexToReg_translate8Bit_returns_C_for_1(self):
self.assertEqual("C", IndexToReg.translate8Bit(1))
def test_IndexToReg_translate8Bit_returns_A_for_7(self):
self.assertEquals("A", IndexToReg.translate8Bit(7))
def test_IndexToReg_translate8Bit_returns_L_for_5(self):
self.assertEquals("L", IndexToReg.translate8Bit(5))
def test_IndexToReg_translate8Bit_returns_H_for_4(self):
self.assertEqual("H", IndexToReg.translate8Bit(4))
def test_IndexToReg_translate8Bit_returns_D_for_2(self):
self.assertEquals("D", IndexToReg.translate8Bit(2))
def test_IndexToReg_translate8Bit_returns_E_for_3(self):
self.assertEqual("E", IndexToReg.translate8Bit(3))
def test_IndexToReg_translate8Bit_returns_E_for_3(self):
self.assertEquals("E", IndexToReg.translate8Bit(3))
def test_IndexToReg_translate8Bit_returns_B_for_0(self):
self.assertEqual("B", IndexToReg.translate8Bit(0))
def test_IndexToReg_translate8Bit_returns_C_for_1(self):
self.assertEquals("C", IndexToReg.translate8Bit(1))