def driveDCmdReady(self):
dut = self.dut
dut.io_d_cmd_ready <= 1
while True:
yield [Edge(dut.io_d_rsp_valid), Edge(dut.io_d_rsp_ready)]
dut.io_d_cmd_ready <= (int(dut.io_d_rsp_valid) == 0
or int(dut.io_d_rsp_ready) == 1)
def _monitor_recv(self):
reset_edge = Edge(self.dut.i_reset)
d_edge = Edge(self.dut.i_d)
clk_edge = Edge(self.dut.i_clk)
ro = ReadOnly()
while True:
yield [reset_edge, clk_edge, d_edge]
yield ro
self._recv(self.dut.o_q.value)
def _monitor_recv(self):
reset_edge = Edge(self.dut.i_reset)
d_edge = Edge(self.dut.i_d)
clk_edge = Edge(self.dut.i_clk)
transaction = __Proj__Transaction()
ro = ReadOnly()
while True:
yield [reset_edge, clk_edge, d_edge]
yield ro
transaction.reset_val = self.dut.i_reset.value
transaction.clk_val = self.dut.i_clk.value
transaction.d_val = self.dut.i_d.value
self._recv(transaction)
def test_edge_identity(dut):
"""
Test that Edge triggers returns the same object each time
"""
re = RisingEdge(dut.clk)
fe = FallingEdge(dut.clk)
e = Edge(dut.clk)
assert re is RisingEdge(dut.clk)
assert fe is FallingEdge(dut.clk)
assert e is Edge(dut.clk)
# check they are all unique
assert len({re, fe, e}) == 3
yield Timer(1)
def validate_mosi_miso_stability(self, test_name):
previous_clk = self.dut.spi_clk
previous_mosi = self.dut.spi_mosi
if self.wires == 4:
previous_miso = self.dut.spi_miso
while True:
v = self.dut.spi_cs_n.value
v_str = "{}".format(v)
# self.dut._log.error("{} - CS_N value: {} Reset value: {}".format(test_name, v_str, self.dut.reset))
if v_str == "0" and self.dut.reset == 0:
if self.dut.spi_clk:
# Clock went high, so capture value
if previous_clk == 0:
previous_mosi = self.dut.spi_mosi
if self.wires == 4:
previous_miso = self.dut.spi_miso
else:
if int(self.dut.spi_mosi) != int(previous_mosi):
raise TestFailure(
"spi.mosi changed while clk was high (was {}, now {})"
.format(previous_mosi, self.dut.spi_mosi))
if self.wires == 4:
if int(self.dut.spi_miso) != int(previous_miso):
raise TestFailure(
"spi.mosi changed while clk was high (was {}, now {})"
.format(previous_miso, self.dut.spi_miso))
previous_clk = self.dut.spi_clk
# else:
# self.dut._log.error("CS_N is Z")
yield Edge(self.dut.clk48)
async def test_singleton_isinstance(dut):
"""
Test that the result of trigger expression have a predictable type
"""
assert isinstance(RisingEdge(dut.clk), RisingEdge)
assert isinstance(FallingEdge(dut.clk), FallingEdge)
assert isinstance(Edge(dut.clk), Edge)
await Timer(1, "ns")
def _wait_reset(self, active_mode=1):
'''
Wait until reset is in an inactive state.
'''
rst = self.rst
if str(rst.value) == 'z' or str(rst.value) == 'x' or int(
rst.value) == active_mode:
yield Edge(rst)
yield NullTrigger()
def start(self):
r_e = RisingEdge(self.clk)
valid_edge = Edge(self.valid)
while True:
yield [valid_edge, r_e]
self.ack <= 0
if self.valid.value.integer == 1:
for i in range(randint(0, self.ack_rand_latency)):
yield r_e
if self.valid.value.integer == 1:
self.ack <= 1
def _wait_for_nsignal(self, signal):
"""This method will return with the specified signal
has hit logic 0. The state will be in the ReadOnly phase
so sim will need to move to NextTimeStep before
registering more callbacks can occour
"""
yield ReadOnly()
while signal.value.integer != 0:
yield Edge(signal)
yield ReadOnly()
yield NextTimeStep()
def _wait_for_nsignal(self, signal):
"""This method will return when the specified signal
has hit logic ``0``. The state will be in the
:class:`~cocotb.triggers.ReadOnly` phase so sim will need
to move to :class:`~cocotb.triggers.NextTimeStep` before
registering more callbacks can occur.
"""
yield ReadOnly()
while signal.value.integer != 0:
yield Edge(signal)
yield ReadOnly()
yield NextTimeStep()
def test_singleton_isinstance(dut):
"""
Test that the result of trigger expression have a predictable type
"""
assert isinstance(RisingEdge(dut.clk), RisingEdge)
assert isinstance(FallingEdge(dut.clk), FallingEdge)
assert isinstance(Edge(dut.clk), Edge)
assert isinstance(NextTimeStep(), NextTimeStep)
assert isinstance(ReadOnly(), ReadOnly)
assert isinstance(ReadWrite(), ReadWrite)
yield Timer(1)
def test_either_edge(dut):
"""Test that either edge can be triggered on"""
dut.clk <= 0
yield Timer(1)
dut.clk <= 1
yield Edge(dut.clk)
if dut.clk.value.integer != 1:
raise TestError("Value should be 0")
yield Timer(10)
dut.clk <= 0
yield Edge(dut.clk)
if dut.clk.value.integer != 0:
raise TestError("Value should be 0")
yield Timer(10)
dut.clk <= 1
yield Edge(dut.clk)
if dut.clk.value.integer != 1:
raise TestError("Value should be 0")
yield Timer(10)
dut.clk <= 0
yield Edge(dut.clk)
if dut.clk.value.integer != 0:
raise TestError("Value should be 0")
yield Timer(10)
dut.clk <= 1
yield Edge(dut.clk)
if dut.clk.value.integer != 1:
raise TestError("Value should be 0")
yield Timer(10)
dut.clk <= 0
yield Edge(dut.clk)
if dut.clk.value.integer != 0:
raise TestError("Value should be 0")
def sequence_test(dut):
""" Chequear que la secuencia sea:
- Flanco de SS
- Length flancos ascendentes del SCLK
- Flanco de SS
"""
cocotb.fork(Clock(dut.AXI_ACLK, period=CLK_PERIOD, units='ns').start())
yield reset(dut)
spi_axi, spi_slave = yield init_spi(dut, 8, 10)
send = cocotb.fork(spi_axi.send_recv(0x55))
ss = Edge(dut.SS)
r_sclk = RisingEdge(dut.SCLK)
timeout = Timer(150, units='us')
yield send.join()
def simulator_signal_triggers(dut):
"""Playing with the Simulator Signals Triggers"""
cocotb.fork(Clock(dut.clk_i, 2).start())
yield reset(dut)
#
for i in range(4):
yield RisingEdge(dut.clk_i)
print_fired(dut, "RisingEdge")
for i in range(4):
yield FallingEdge(dut.clk_i)
print_fired(dut, "FallingEdge")
for i in range(4):
yield Edge(dut.clk_i)
print_fired(dut, "Edge")
for i in range(4):
yield ClockCycles(dut.clk_i, 3)
print_fired(dut, "ClockCycle")
async def peripheral_return_response(self, sdo_binstr):
cs_n_edge = Edge(
self.io['cs_n']) if self.io['cs_n'] is not None else None
if self.io[
'cs_n'] is not None: # some 2-wire point-to-points do not have cs
await FallingEdge(self.io['cs_n'])
if self.lsb_first:
sdo_binstr = sdo_binstr[::-1] # data bits sent from left to right
send_edge = FallingEdge(self.io['sclk'])
if self.mode in [0, 2]:
send_edge = RisingEdge(self.io['sclk'])
self.io['sdo'] <= int(sdo_binstr[0], 2) # drive before 1st clock
sdo_binstr = sdo_binstr[1:] # remove bit 0 (left-most bit)
while sdo_binstr != "":
edge = await First(cs_n_edge, send_edge)
if edge == cs_n_edge:
break
self.io['sdo'] <= int(sdo_binstr[0], 2)
sdo_binstr = sdo_binstr[1:] # remove bit 0 (left-most bit)
async def peripheral_monitor(self):
cs_n_edge = Edge(
self.io['cs_n']) if self.io['cs_n'] is not None else None
sdi_binstr = ""
if self.io[
'cs_n'] is not None: # some 2-wire point-to-points do not have cs
await FallingEdge(self.io['cs_n'])
capture_edge = FallingEdge(self.io['sclk'])
if self.mode in [0, 3]:
capture_edge = RisingEdge(self.io['sclk'])
while len(sdi_binstr) < self.size:
edge = await capture_edge
if edge == cs_n_edge:
break
elif edge == capture_edge:
sdi_binstr = sdi_binstr + self.io['sdi'].value.binstr
if self.lsb_first:
sdi_binstr = sdi_binstr[::-1]
return sdi_binstr
def combEvent(self):
while True:
yield Edge(self.ahb.HREADYOUT)
self.doComb()
def pinWatcher(self, driver):
while True:
yield Edge(driver)
self.evaluate()
def _synchronize(self):
'''
Instead of synchronzing on a control signal, wait until the data changes.
'''
yield [Edge(handle) for sig, handle in vars(self).items()]
def txToRxBypass(dut):
while True:
dut.io_uart_uart_rxd <= int(dut.io_uart_uart_txd)
yield Edge(dut.io_uart_uart_txd)
async def drive_data(self):
while True:
await Combine(Edge(self.sig_data_out), Edge(self.sig_data))
if self.slave_en == 1:
self.sig_data <= self.sig_data_out
def acknowledgment(self):
while True:
yield Edge(self.rdy)
self.ack <= self.rdy.value.integer
def loopback(self):
self.miso <= self.mosi.value
while True:
yield Edge(self.mosi)
self.miso <= self.mosi.value
