def main():
# Add options
parser = optparse.OptionParser()
Options.addCommonOptions(parser)
Options.addFSOptions(parser)
(options, args) = parser.parse_args()
system = build_switch(options)
root = Root(full_system = True, system = system)
Simulation.run(options, root, None, None)
# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
# is actually used only by the caches connected to the CPU.
system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
voltage_domain =
system.cpu_voltage_domain)
# All cpus belong to a common cpu_clk_domain, therefore running at a common
# frequency.
for cpu in system.cpu:
cpu.clk_domain = system.cpu_clk_domain
# BaseCPU no longer has default values for the BaseCPU.isa
# createThreads() is needed to fill in the cpu.isa
for cpu in system.cpu:
cpu.createThreads()
# Assign input trace files to the Trace CPU
system.cpu.instTraceFile=options.inst_trace_file
system.cpu.dataTraceFile=options.data_trace_file
# Configure the classic memory system options
MemClass = Simulation.setMemClass(options)
system.membus = SystemXBar()
system.system_port = system.membus.slave
CacheConfig.config_cache(options, system)
MemConfig.config_mem(options, system)
root = Root(full_system = False, system = system)
Simulation.run(options, root, system, FutureClass)
options.ethernet_linkspeed,
options.ethernet_linkdelay,
options.etherdump);
elif len(bm) == 1:
root = Root(full_system=True, system=test_sys)
else:
print("Error I don't know how to create more than 2 systems.")
sys.exit(1)
if options.timesync:
root.time_sync_enable = True
if options.frame_capture:
VncServer.frame_capture = True
if buildEnv['TARGET_ISA'] == "arm" and not options.bare_metal \
and not options.dtb_filename:
if options.machine_type not in ["VExpress_GEM5", "VExpress_GEM5_V1"]:
warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \
"platforms, unless custom hardware models have been equipped "\
"with generation functionality.")
# Generate a Device Tree
for sysname in ('system', 'testsys', 'drivesys'):
if hasattr(root, sysname):
sys = getattr(root, sysname)
sys.generateDtb(m5.options.outdir, '%s.dtb' % sysname)
Simulation.setWorkCountOptions(test_sys, options)
Simulation.run(options, root, test_sys, FutureClass)
if args.timesync:
root.time_sync_enable = True
if args.frame_capture:
VncServer.frame_capture = True
if buildEnv['TARGET_ISA'] == "arm" and not args.bare_metal \
and not args.dtb_filename:
if args.machine_type not in [
"VExpress_GEM5", "VExpress_GEM5_V1", "VExpress_GEM5_V2",
"VExpress_GEM5_Foundation"
]:
warn("Can only correctly generate a dtb for VExpress_GEM5_* " \
"platforms, unless custom hardware models have been equipped "\
"with generation functionality.")
# Generate a Device Tree
for sysname in ('system', 'testsys', 'drivesys'):
if hasattr(root, sysname):
sys = getattr(root, sysname)
sys.workload.dtb_filename = \
os.path.join(m5.options.outdir, '%s.dtb' % sysname)
sys.generateDtb(sys.workload.dtb_filename)
if args.wait_gdb:
test_sys.workload.wait_for_remote_gdb = True
Simulation.setWorkCountOptions(test_sys, args)
Simulation.run(args, root, test_sys, FutureClass)
core_set = nf_core_mapping['dpi-queue']
for i, core_id in enumerate(core_set):
if i == 0:
continue
system.cpu[core_id].icache.mem_side = system.membus.slave
system.cpu[core_id].dcache.mem_side = system.membus.slave
system.cpu[core_id].itb.walker.port = system.membus.slave
system.cpu[core_id].dtb.walker.port = system.membus.slave
# print(system.cpu[core_id].icache.mem_side, system.cpu[core_id].dcache.mem_side)
system.cpu[core_id].dcache.size = "8kB"
system.cpu[core_id].dcache.assoc = 1
if 'spmc' in nf_core_mapping:
core_set = nf_core_mapping['spmc']
for i, core_id in enumerate(core_set):
if i == 0:
continue
system.cpu[core_id].icache.mem_side = system.membus.slave
system.cpu[core_id].dcache.mem_side = system.membus.slave
system.cpu[core_id].itb.walker.port = system.membus.slave
system.cpu[core_id].dtb.walker.port = system.membus.slave
# print(system.cpu[core_id].icache.mem_side, system.cpu[core_id].dcache.mem_side)
system.cpu[core_id].dcache.size = "8kB"
system.cpu[core_id].dcache.assoc = 1
# import sys
# sys.exit()
root = Root(full_system=False, system=system)
Simulation.run(options, root, system, FutureClass)
options.dist_sync_repeat, options.dist_sync_start,
options.ethernet_linkspeed, options.ethernet_linkdelay,
options.etherdump)
elif len(bm) == 1:
root = Root(full_system=True, system=test_sys)
else:
print("Error I don't know how to create more than 2 systems.")
sys.exit(1)
if options.timesync:
root.time_sync_enable = True
if options.frame_capture:
VncServer.frame_capture = True
if buildEnv['TARGET_ISA'] == "arm" and not options.bare_metal \
and not options.dtb_filename:
if options.machine_type not in ["VExpress_GEM5", "VExpress_GEM5_V1"]:
warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \
"platforms, unless custom hardware models have been equipped "\
"with generation functionality.")
# Generate a Device Tree
for sysname in ('system', 'testsys', 'drivesys'):
if hasattr(root, sysname):
sys = getattr(root, sysname)
sys.generateDtb(m5.options.outdir, '%s.dtb' % sysname)
Simulation.setWorkCountOptions(test_sys, options)
Simulation.run(options, root, test_sys, FutureClass)
system.workload.dtb_filename = args.dtb_filename
else:
generateDtb(system)
system.workload.dtb_filename = path.join(m5.options.outdir,
'device.dtb')
# Default DTB address if bbl is bulit with --with-dts option
system.workload.dtb_addr = 0x87e00000
# Linux boot command flags
if args.command_line:
system.workload.command_line = args.command_line
else:
kernel_cmd = ["console=ttyS0", "root=/dev/vda", "ro"]
system.workload.command_line = " ".join(kernel_cmd)
# ---------------------------- Default Setup --------------------------- #
if args.elastic_trace_en and args.checkpoint_restore == None and \
not args.fast_forward:
CpuConfig.config_etrace(CPUClass, system.cpu, args)
CacheConfig.config_cache(args, system)
MemConfig.config_mem(args, system)
root = Root(full_system=True, system=system)
Simulation.setWorkCountOptions(system, args)
Simulation.run(args, root, system, FutureClass)
# to other gem5 instances
switch.portlink = [
DistEtherLink(speed=options.ethernet_linkspeed,
delay=options.ethernet_linkdelay,
dist_rank=options.dist_rank,
dist_size=options.dist_size,
server_name=options.dist_server_name,
server_port=options.dist_server_port,
sync_start=options.dist_sync_start,
sync_repeat=options.dist_sync_repeat,
is_switch=True,
num_nodes=options.dist_size)
for i in xrange(options.dist_size)
]
for (i, link) in enumerate(switch.portlink):
link.int0 = switch.interface[i]
return switch
# Add options
parser = optparse.OptionParser()
Options.addCommonOptions(parser)
Options.addFSOptions(parser)
(options, args) = parser.parse_args()
system = build_switch(options)
root = Root(full_system=True, system=system)
Simulation.run(options, root, None, None)
# instantiate an EtherSwitch
switch = EtherSwitch()
# instantiate distEtherLinks to connect switch ports
# to other gem5 instances
switch.portlink = [DistEtherLink(speed = options.ethernet_linkspeed,
delay = options.ethernet_linkdelay,
dist_rank = options.dist_rank,
dist_size = options.dist_size,
server_name = options.dist_server_name,
server_port = options.dist_server_port,
sync_start = options.dist_sync_start,
sync_repeat = options.dist_sync_repeat,
is_switch = True,
num_nodes = options.dist_size)
for i in xrange(options.dist_size)]
for (i, link) in enumerate(switch.portlink):
link.int0 = switch.interface[i]
return switch
# Add options
parser = optparse.OptionParser()
Options.addCommonOptions(parser)
Options.addFSOptions(parser)
(options, args) = parser.parse_args()
system = build_switch(options)
root = Root(full_system = True, system = system)
Simulation.run(options, root, None, None)
