def run_system_with_cpu(
process,
options,
output_dir,
warmup_cpu_class=None,
warmup_instructions=0,
real_cpu_create_function=lambda cpu_id: DerivO3CPU(cpu_id=cpu_id),
):
# Override the -d outdir --outdir option to gem5
m5.options.outdir = output_dir
m5.core.setOutputDir(m5.options.outdir)
m5.stats.reset()
max_tick = options.abs_max_tick
if options.rel_max_tick:
max_tick = options.rel_max_tick
elif options.maxtime:
max_tick = int(options.maxtime * 1000 * 1000 * 1000 * 1000)
eprint("Simulating until tick=%s" % (max_tick))
real_cpus = [real_cpu_create_function(0)]
mem_mode = real_cpus[0].memory_mode()
if warmup_cpu_class:
warmup_cpus = [warmup_cpu_class(cpu_id=0)]
warmup_cpus[0].max_insts_any_thread = warmup_instructions
else:
warmup_cpus = real_cpus
system = System(cpu=warmup_cpus,
mem_mode=mem_mode,
mem_ranges=[AddrRange(options.mem_size)],
cache_line_size=options.cacheline_size)
system.multi_thread = False
system.voltage_domain = VoltageDomain(voltage=options.sys_voltage)
system.clk_domain = SrcClockDomain(clock=options.sys_clock,
voltage_domain=system.voltage_domain)
system.cpu_voltage_domain = VoltageDomain()
system.cpu_clk_domain = SrcClockDomain(
clock=options.cpu_clock, voltage_domain=system.cpu_voltage_domain)
system.cache_line_size = options.cacheline_size
if warmup_cpu_class:
for cpu in real_cpus:
cpu.clk_domain = system.cpu_clk_domain
cpu.workload = process
cpu.system = system
cpu.switched_out = True
cpu.createThreads()
system.switch_cpus = real_cpus
for cpu in system.cpu:
cpu.clk_domain = system.cpu_clk_domain
cpu.workload = process
if options.prog_interval:
cpu.progress_interval = options.prog_interval
cpu.createThreads()
MemClass = Simulation.setMemClass(options)
system.membus = SystemXBar()
system.system_port = system.membus.slave
system.cpu[0].connectAllPorts(system.membus)
MemConfig.config_mem(options, system)
root = Root(full_system=False, system=system)
m5.options.outdir = output_dir
m5.instantiate(None) # None == no checkpoint
if warmup_cpu_class:
eprint("Running warmup with warmup CPU class (%d instrs.)" %
(warmup_instructions))
eprint("Starting simulation")
exit_event = m5.simulate(max_tick)
if warmup_cpu_class:
max_tick -= m5.curTick()
m5.stats.reset()
debug_print("Finished warmup; running real simulation")
m5.switchCpus(system, real_cpus)
exit_event = m5.simulate(max_tick)
eprint("Done simulation @ tick = %s: %s" %
(m5.curTick(), exit_event.getCause()))
m5.stats.dump()
assert(options.num_cpus == len(system.ruby._cpu_ports))
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
for i in xrange(np):
ruby_port = system.ruby._cpu_ports[i]
# Create the interrupt controller and connect its ports to Ruby
# Note that the interrupt controller is always present but only
# in x86 does it have message ports that need to be connected
system.cpu[i].createInterruptController()
# Connect the cpu's cache ports to Ruby
system.cpu[i].icache_port = ruby_port.slave
system.cpu[i].dcache_port = ruby_port.slave
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].interrupts[0].pio = ruby_port.master
system.cpu[i].interrupts[0].int_master = ruby_port.slave
system.cpu[i].interrupts[0].int_slave = ruby_port.master
system.cpu[i].itb.walker.port = ruby_port.slave
system.cpu[i].dtb.walker.port = ruby_port.slave
else:
MemClass = Simulation.setMemClass(options)
system.membus = SystemXBar()
system.system_port = system.membus.slave
CacheConfig.config_cache(options, system)
MemConfig.config_mem(options, system)
root = Root(full_system = False, system = system)
Simulation.run(options, root, system, FutureClass)
# Add args
parser = argparse.ArgumentParser()
Options.addCommonOptions(parser)
Options.addFSOptions(parser)
# Add the ruby specific and protocol specific args
if '--ruby' in sys.argv:
Ruby.define_options(parser)
args = parser.parse_args()
# system under test can be any CPU
(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(args)
# Match the memories with the CPUs, based on the options for the test system
TestMemClass = Simulation.setMemClass(args)
if args.benchmark:
try:
bm = Benchmarks[args.benchmark]
except KeyError:
print("Error benchmark %s has not been defined." % args.benchmark)
print("Valid benchmarks are: %s" % DefinedBenchmarks)
sys.exit(1)
else:
if args.dual:
bm = [
SysConfig(disks=args.disk_image,
rootdev=args.root_device,
mem=args.mem_size,
os_type=args.os_type),
# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
# is actually used only by the caches connected to the CPU.
system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
voltage_domain =
system.cpu_voltage_domain)
# All cpus belong to a common cpu_clk_domain, therefore running at a common
# frequency.
for cpu in system.cpu:
cpu.clk_domain = system.cpu_clk_domain
# BaseCPU no longer has default values for the BaseCPU.isa
# createThreads() is needed to fill in the cpu.isa
for cpu in system.cpu:
cpu.createThreads()
# Assign input trace files to the Trace CPU
system.cpu.instTraceFile=options.inst_trace_file
system.cpu.dataTraceFile=options.data_trace_file
# Configure the classic memory system options
MemClass = Simulation.setMemClass(options)
system.membus = SystemXBar()
system.system_port = system.membus.slave
CacheConfig.config_cache(options, system)
MemConfig.config_mem(options, system)
root = Root(full_system = False, system = system)
Simulation.run(options, root, system, FutureClass)
def run_system_with_cpu(
process,
options,
output_dir,
warmup_instructions=0,
):
warmup = True
# Override the -d outdir --outdir option to gem5
m5.options.outdir = output_dir
m5.core.setOutputDir(m5.options.outdir)
m5.stats.reset()
max_tick = options.abs_max_tick
if options.rel_max_tick:
max_tick = options.rel_max_tick
elif options.maxtime:
max_tick = int(options.maxtime * 1000 * 1000 * 1000 * 1000)
eprint("Simulating until tick=%s" % (max_tick))
# DerivO3CPU is the configurable out-of-order CPU model supplied by gem5
the_cpu = DerivO3CPU(cpu_id=0, switched_out=warmup)
icache = L1_ICache(size=options.l1i_size, assoc=options.l1i_assoc)
dcache = L1_DCache(size=options.l1d_size, assoc=options.l1d_assoc)
the_cpu.branchPred = LocalBP()
# Parameter values
the_cpu.numROBEntries = options.ROB
the_cpu.numIQEntries = options.IQ
real_cpus = [the_cpu]
mem_mode = real_cpus[0].memory_mode()
if warmup:
the_w_cpu = TimingSimpleCPU(cpu_id=0)
the_w_cpu.branchPred = LocalBP()
# Parameter values
the_w_cpu[0].addPrivateSplitL1Caches(icache, dcache, None, None)
the_w_cpu[0].createInterruptController()
warmup_cpus = [the_w_cpu]
if warmup_instructions:
warmup_cpus[0].max_insts_any_thread = warmup_instructions
else:
warmup_cpus = real_cpus
system = System(cpu=warmup_cpus,
mem_mode=mem_mode,
mem_ranges=[AddrRange(options.mem_size)],
cache_line_size=options.cacheline_size)
system.multi_thread = False
system.voltage_domain = VoltageDomain(voltage=options.sys_voltage)
system.clk_domain = SrcClockDomain(clock=options.sys_clock,
voltage_domain=system.voltage_domain)
system.cpu_voltage_domain = VoltageDomain()
system.cpu_clk_domain = SrcClockDomain(
clock=options.cpu_clock, voltage_domain=system.cpu_voltage_domain)
system.cache_line_size = options.cacheline_size
cache_line_size = options.cacheline_size
for cpu in system.cpu:
cpu.clk_domain = system.cpu_clk_domain
cpu.workload = process
if options.prog_interval:
cpu.progress_interval = options.prog_interval
cpu.createThreads()
MemClass = Simulation.setMemClass(options)
system.membus = SystemXBar()
system.system_port = system.membus.slave
system.cpu[0].connectAllPorts(system.membus)
MemConfig.config_mem(options, system)
root = Root(full_system=False, system=system)
if warmup:
for cpu in real_cpus:
cpu.clk_domain = system.cpu_clk_domain
cpu.workload = process
cpu.system = system
cpu.switched_out = True
cpu.createThreads()
root.switch_cpus = real_cpus
m5.options.outdir = output_dir
m5.instantiate(None) # None == no checkpoint
if warmup:
eprint("Running warmup with warmup CPU class ({} instrs.)".format(
warmup_instructions))
eprint("Starting simulation")
exit_event = m5.simulate(max_tick)
eprint("exit_event: {}".format(exit_event))
if warmup:
max_tick -= m5.curTick()
m5.stats.reset()
eprint("Finished warmup; running real simulation")
m5.switchCpus(system, list(zip(warmup_cpus, real_cpus)))
exit_event = m5.simulate(max_tick)
eprint("Done simulation @ tick = %s: %s" %
(m5.curTick(), exit_event.getCause()))
m5.stats.dump()
