def test_ise():
prj = Project('ise')
assert get_part(prj) == "xc7k160t-3-fbg484"
prj.set_part('XC6SLX9-2-CSG324')
assert get_part(prj) == "xc6slx9-2-csg324"
prj.set_part('XC6SLX9-2L-CSG324')
assert get_part(prj) == "xc6slx9-2l-csg324"
prj.set_part('XC6SLX9-CSG324-3')
assert get_part(prj) == "xc6slx9-3-csg324"
def test_libero():
prj = Project('libero')
assert get_part(prj) == "mpf100t-1-fcg484"
prj.set_part('m2s010-3-tq144')
assert get_part(prj) == "m2s010-3-tq144"
prj.set_part('m2s010-tq144-2')
assert get_part(prj) == "m2s010-2-tq144"
prj.set_part('m2s010-tq144')
assert get_part(prj) == "m2s010-std-tq144"
from fpga.project import Project
logging.basicConfig()
parser = argparse.ArgumentParser()
parser.add_argument(
'--action', choices=['generate', 'transfer', 'all'], default='generate',
)
parser.add_argument(
'--lang', choices=['verilog', 'vhdl'], default='verilog',
)
args = parser.parse_args()
prj = Project('openflow')
prj.set_outdir('../../build/icestorm-{}'.format(args.lang))
prj.set_part('hx4k-tq144')
if args.lang == 'verilog':
prj.add_path('../../hdl/headers1')
prj.add_path('../../hdl/headers2')
prj.add_files('../../hdl/blinking.v')
prj.add_files('../../hdl/top.v')
else: # args.lang == 'vhdl'
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.add_files('*.pcf')
prj.set_top('Top')
if args.action in ['generate', 'all']:
parser = argparse.ArgumentParser()
parser.add_argument(
'--action',
choices=['generate', 'transfer', 'all'],
default='generate',
)
parser.add_argument(
'--lang',
choices=['verilog', 'vhdl'],
default='verilog',
)
args = parser.parse_args()
prj = Project('yosys-vivado')
prj.set_outdir('../../build/yosys-vivado-{}'.format(args.lang))
prj.set_part('xc7z010-1-clg400')
if args.lang == 'verilog':
prj.add_path('../../hdl/headers1')
prj.add_path('../../hdl/headers2')
prj.add_files('../../hdl/blinking.v')
prj.add_files('../../hdl/top.v')
else: # args.lang == 'vhdl'
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.add_files('../vivado/zybo.xdc')
prj.set_top('Top')
if args.action in ['generate', 'all']:
def build(prj):
prj.add_files(str(ROOT.parent / 'src' / '*.vhd'), 'examples')
prj.set_top('demo')
try:
prj.generate()
#prj.transfer()
except Exception as e:
print('{} ({})'.format(type(e).__name__, e))
for toolchain in ['vivado', 'yosys']:
if toolchain == 'vivado' and which('vivado'):
prj = Project('vivado', 'vhdl-cfg_vivado')
prj.set_outdir(str(ROOT / 'build' / 'vivado'))
prj.set_part('xc7z020clg400-1') # PYNQ-Z1
#! TODO I/O constraints file is missing
build(prj)
continue
if toolchain == 'yosys' and which('yosys'):
prj = Project('yosys', 'vhdl-cfg_yosys')
prj.set_outdir(str(ROOT / 'build' / 'yosys'))
#! TODO Is this the expected part format for Lattice devices?
prj.set_part('hx1k-tq144') # Icestick
#! TODO I/O constraints file is missing
choices=['generate', 'transfer', 'all'],
default='generate')
parser.add_argument('--lang', choices=['verilog', 'vhdl'], default='verilog')
parser.add_argument('--board',
choices=['orangecrab', 'ecp5evn'],
default='orangecrab')
args = parser.parse_args()
BOARDS = {
'orangecrab': ['25k-CSFBGA285', 'orangecrab_r0.2.lpf'],
'ecp5evn': ['um5g-85k-CABGA381', 'ecp5evn.lpf']
}
prj = Project('openflow')
prj.set_outdir('../../build/prjtrellis-{}-{}'.format(args.board, args.lang))
prj.set_part(BOARDS[args.board][0])
if args.lang == 'verilog':
prj.add_path('../../hdl/headers1')
prj.add_path('../../hdl/headers2')
prj.add_files('../../hdl/blinking.v')
prj.add_files('../../hdl/top.v')
else: # args.lang == 'vhdl'
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.add_files(BOARDS[args.board][1])
prj.set_top('Top')
if args.action in ['generate', 'all']:
from fpga.project import Project
logging.basicConfig()
parser = argparse.ArgumentParser()
parser.add_argument(
'--action', choices=['generate', 'transfer', 'all'], default='generate',
)
parser.add_argument(
'--lang', choices=['verilog', 'vhdl'], default='verilog',
)
args = parser.parse_args()
prj = Project('yosys-ise')
prj.set_outdir('../../build/yosys-ise-{}'.format(args.lang))
prj.set_part('XC6SLX9-2-CSG324')
if args.lang == 'verilog':
prj.add_path('../../hdl/headers1')
prj.add_path('../../hdl/headers2')
prj.add_files('../../hdl/blinking.v')
prj.add_files('../../hdl/top.v')
else: # args.lang == 'vhdl'
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.add_files('../ise/s6micro.ucf')
prj.set_top('Top')
if args.action in ['generate', 'all']:
import logging
from fpga.project import Project
logging.basicConfig()
parser = argparse.ArgumentParser()
parser.add_argument(
'--action',
choices=['generate', 'transfer', 'all'],
default='generate',
)
args = parser.parse_args()
prj = Project('quartus')
prj.set_part('5CSEBA6U23I7')
prj.set_outdir('../../build/quartus')
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.set_top('Top')
prj.add_files('de10nano.sdc')
prj.add_files('de10nano.tcl')
if args.action in ['generate', 'all']:
try:
prj.generate()
except RuntimeError:
print('ERROR:generate:Quartus not found')
import logging
from fpga.project import Project
logging.basicConfig()
parser = argparse.ArgumentParser()
parser.add_argument(
'--action',
choices=['generate', 'transfer', 'all'],
default='generate',
)
args = parser.parse_args()
prj = Project('libero')
prj.set_part('m2s010-1-tq144')
prj.set_outdir('../../build/libero')
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.set_top('Top')
prj.add_files('mkr.pdc')
prj.add_files('mkr.sdc')
if args.action in ['generate', 'all']:
try:
prj.generate()
except RuntimeError:
print('ERROR:generate:Libero not found')