def test_files():
prj = Project()
prj.set_top(get_pathfile('../hdl/fakes/top.vhdl'))
assert prj.tool.top == "Top1"
prj.set_top(get_pathfile('../hdl/fakes/top.v'))
assert prj.tool.top == "Top1"
prj.set_top(get_pathfile('../README.md'))
assert prj.tool.top == "UNDEFINED"
args = parser.parse_args()
prj = Project('openflow')
prj.set_outdir('../../build/icestorm-{}'.format(args.lang))
prj.set_part('hx4k-tq144')
if args.lang == 'verilog':
prj.add_path('../../hdl/headers1')
prj.add_path('../../hdl/headers2')
prj.add_files('../../hdl/blinking.v')
prj.add_files('../../hdl/top.v')
else: # args.lang == 'vhdl'
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.add_files('*.pcf')
prj.set_top('Top')
if args.action in ['generate', 'all']:
try:
prj.generate()
except RuntimeError:
print('ERROR:generate:Docker not found')
if args.action in ['transfer', 'all']:
try:
prj.transfer()
except RuntimeError:
print('ERROR:transfer:Docker not found')
"""PyFPGA example about Memory Content Files inclusion.
This example is mainly used as a test of this feature through the different
tools.
"""
import logging
from fpga.project import Project, TOOLS
logging.basicConfig()
for hdl in ['vhdl', 'verilog']:
for tool in TOOLS:
if tool == 'ghdl' and hdl == 'verilog':
continue
PRJ = Project(tool)
PRJ.set_outdir('../../build/multi/memory/%s/%s' % (tool, hdl))
if hdl == 'vhdl':
PRJ.add_files('../../hdl/ram.vhdl')
else:
PRJ.add_files('../../hdl/ram.v')
PRJ.set_top('ram')
try:
PRJ.generate(to_task='syn')
except RuntimeError:
print('ERROR:generate:{} not found'.format(tool))
def test_names():
prj = Project()
prj.set_top('test1')
assert prj.tool.top == "test1"
prj.set_top('test2')
assert prj.tool.top == "test2"
"""PyFPGA Multi Vendor VHDL example.
The main idea of a multi-vendor project is to implements the same HDL code
with different tools, to make comparisons. The project name is not important
and the default devices are used.
"""
import logging
from fpga.project import Project, TOOLS
logging.basicConfig()
for tool in TOOLS:
PRJ = Project(tool)
PRJ.set_outdir('../../build/multi/vhdl/%s' % tool)
PRJ.add_files('../../hdl/blinking.vhdl', library='examples')
PRJ.add_files('../../hdl/examples_pkg.vhdl', library='examples')
PRJ.add_files('../../hdl/top.vhdl')
PRJ.set_top('Top')
try:
PRJ.generate(to_task='syn')
except RuntimeError:
print('ERROR:generate:{} not found'.format(tool))
def main():
"""Solves the main functionality of this helper."""
# Parsing the command-line.
parser = argparse.ArgumentParser(description=__doc__)
parser.add_argument('-v',
'--version',
action='version',
version='v{}'.format(version))
parser.add_argument('project',
metavar='PRJFILE',
help='a vendor project file')
parser.add_argument('--run',
metavar='TASK',
choices=TASKS[1:len(TASKS)],
default='bit',
help='task to perform [{}] ({})'.format(
'bit', " | ".join(TASKS[1:len(TASKS)])))
parser.add_argument('--clean',
action='store_true',
help='clean the generated project files')
args = parser.parse_args()
# Detecting a Project file
tool_per_ext = {
'.xise': 'ise',
'.prjx': 'libero',
'.qpf': 'quartus',
'.xpr': 'vivado'
}
if not os.path.exists(args.project):
sys.exit('Project file not found')
outdir = os.path.dirname(args.project)
project, extension = os.path.splitext(args.project)
project = os.path.basename(project)
tool = ''
if extension in tool_per_ext:
tool = tool_per_ext[extension]
print('{} Project file found.'.format(tool))
else:
sys.exit('Unknown Project file extension')
# Solving with PyFPGA
prj = Project(tool, project=project, relative_to_script=False)
prj.set_outdir(outdir)
prj.set_top(project)
try:
if args.clean:
prj.clean()
else:
prj.generate(args.run, 'syn')
except RuntimeError:
logging.error('{} not found'.format(tool))
except Exception as e:
sys.exit('{} ({})'.format(type(e).__name__, e))
set_property strategy "Flow_PerfOptimized_high" $obj
set_property "steps.synth_design.args.fanout_limit" "400" $obj
set_property "steps.synth_design.args.keep_equivalent_registers" "1" $obj
set_property "steps.synth_design.args.resource_sharing" "off" $obj
set_property "steps.synth_design.args.no_lc" "1" $obj
set_property "steps.synth_design.args.shreg_min_size" "5" $obj
set obj [get_runs impl_1]
set_property strategy "Performance_Explore" $obj
set_property "steps.opt_design.args.directive" "Explore" $obj
set_property "steps.place_design.args.directive" "Explore" $obj
set_property "steps.phys_opt_design.is_enabled" "1" $obj
set_property "steps.phys_opt_design.args.directive" "Explore" $obj
set_property "steps.route_design.args.directive" "Explore" $obj
"""
}
}
for tool in commands:
for strategy in commands[tool]:
PRJ = Project(tool)
PRJ.set_outdir('../../build/hooks/%s-%s' % (tool, strategy))
PRJ.add_files('../../hdl/blinking.vhdl')
PRJ.set_top('Blinking')
PRJ.add_hook('puts "Appling {} optimizations"'.format(strategy),
'project')
PRJ.add_hook(commands[tool][strategy], 'project')
try:
PRJ.generate(to_task='syn')
except RuntimeError:
print('ERROR:generate:{} not found'.format(tool))
parser = argparse.ArgumentParser()
parser.add_argument(
'--action',
choices=['generate', 'transfer', 'all'],
default='generate',
)
args = parser.parse_args()
prj = Project('vivado')
prj.set_part('xc7z010-1-clg400')
prj.set_outdir('../../build/vivado')
prj.set_param('FREQ', '125000000')
prj.add_files('../../hdl/blinking.vhdl')
prj.add_files('zybo.xdc')
prj.set_top('Blinking')
if args.action in ['generate', 'all']:
try:
prj.generate()
except RuntimeError:
print('ERROR:generate:Vivado not found')
if args.action in ['transfer', 'all']:
try:
prj.transfer('fpga')
except RuntimeError:
print('ERROR:transfer:Vivado not found')
