def __init__(self, parent: Module, source: Wire, delay: int):
super().__init__("{}_v_buffer".format(source.name), parent)
buf_out = parent.create_wire()
org_post = set(source.post)
for p in org_post:
p.unbind()
p.bind(buf_out)
self._input = PinIn("v_bfr_in", self, source)
self._output = PinOut("v_bfr_out", self, buf_out)
self._delay = delay
def insert_port(host: Module):
for port_in in host.inputs:
source_port = set(port_in.post).pop()
interim = host.create_wire()
source_port.unbind()
source_port.bind(interim)
or_a = host.create_wire()
or_b = host.create_wire()
host.add_instance("{}_port_xnor_or".format(port_in.name),
cell_lib.get("or_bb"), {
'a': or_a.name,
'b': or_b.name,
'c': interim.name
})
xnor_a = host.create_wire()
xnor_b = host.create_wire()
host.add_instance("{}_port_xnor_and".format(port_in.name),
cell_lib.get("and_bb"), {
'a': xnor_a.name,
'b': xnor_b.name,
'c': or_a.name
})
host.add_instance("{}_port_xnor_and_ii".format(port_in.name),
cell_lib.get("and_ii"), {
'a': xnor_a.name,
'b': xnor_b.name,
'c': or_b.name
})
xnor_b_end = xnor_b
for i in range(4):
xnor_b = host.create_wire()
host.register_instance(cell_lib.get_buffer().instantiate(
"{}_bfr_after".format(xnor_b.name), host,
[xnor_b, xnor_b_end]))
xnor_b_end = xnor_b
host.register_instance(
cell_lib.get_splitter(2).instantiate(
"{}_port_splitter".format(port_in.name), host,
[port_in, xnor_a, xnor_b]))
def __init__(self,
parent: Module,
source: Wire,
child_wires: Dict[Wire, int] = None):
super().__init__("{}_v_fanout".format(source.name), parent)
self._before = 0
self._tracker = 0
self._outputs = set()
self._after = dict()
if child_wires is None:
org_post = set(source.post)
for p in org_post:
p.unbind()
split_out_wire = parent.create_wire()
p.bind(split_out_wire)
self._add_wire(split_out_wire)
else:
for p in child_wires.keys():
self._add_wire(p, child_wires[p])
self._input = PinIn("v_fanout_in", self, source)
def majority_mapping_single(lib: Library, mod: Module, target: Wire,
border: list, selection: tuple, pre_wire: list,
final: list):
internals = list()
if len(border) != 3 or len(selection) != 3 or len(final) != 3 or len(
pre_wire) != 3:
return
value = 232
for i in range(3):
if selection[i] == 0:
value = 8
del final[i]
continue
if selection[i] == 1:
value = 14
del final[i]
continue
if selection[i] < 8:
internals.append(border[i])
if majority_primary_truth[selection[i]] == 1:
final[i] = not final[i]
else:
if pre_wire[i] is not None:
internals.append(pre_wire[i])
else:
new_wire = mod.create_wire()
internals.append(new_wire)
truth = majority_primary_truth[selection[i]]
start_border = [
border[x] for x in majority_primary_inputs[selection[i]]
]
gate_mapping(mod, new_wire, start_border, truth, lib)
bn = BooleanNode(target.name)
inputs = [BooleanVariable(x.name) for x in internals]
bn.assign(inputs, value)
for i in range(len(final)):
if not final[i]:
bn.negate(inputs[i].name)
gate_mapping(mod, target, internals, bn.truth_value, lib)
