def float_net_checker(module: Module):
net_names = module.nets
passed = True
for net_name in net_names:
net = module.get_net(net_name)
if not isinstance(net, PortIn) and not isinstance(net, PortOut):
if len(net.post) == 0 or net.source is None:
passed = False
print("isolated net found at {}".format(net_name))
if passed:
print("\nNetlist check complete")
def missing_instance_test(module: Module):
net_names = module.nets
inst_names = module.instance_names
passed = True
for net_name in net_names:
net = module.get_net(net_name)
if net.source_instance is not None:
if net.source_instance.name not in inst_names:
passed = False
print(
"net {} source instance {} not recorded in module.".format(
net_name, net.source_instance.name))
if passed:
print("\nInstance check passed")
def splitter_checker(module: Module):
net_names = module.nets
passed = True
falied_instance = set()
for net_name in net_names:
net = module.get_net(net_name)
if len(net.post) > 1:
passed = False
print("Unresolved fan-out found at net {}, fan out num {}".format(
net_name, len(net.post)))
for ins in net.post:
if isinstance(ins.parent, Distributor):
falied_instance.add(ins.parent.name)
if passed:
print("\nfan out check passed.")
return falied_instance
def flow_checker(module: Module):
module.reset_delay()
net_names = module.nets
passed = True
for net_name in net_names:
net = module.get_net(net_name)
if len(net.get_parents()) >= 1:
delays = {module.get_delay(pre.name) for pre in net.get_parents()}
if len(delays) == 1:
continue
else:
passed = False
print("\nUnequal path found at node {}".format(net_name))
delays = {module.delays.values()}
if len(delays) != 1:
print("\nOutputs delay not equal")
passed = False
if passed:
print("\nEven data path test passed.")
def majority_feasible_checker(target: Wire, maj_mod: Module):
if len(target.get_parents()) != 2:
return {}
level = 4
parents = target.get_parents()
lp = parents.pop().get_ancestors(level)
rp = parents.pop().get_ancestors(level)
if isinstance(lp, dict):
print(lp)
if isinstance(rp, dict):
print(rp)
total = set.union(lp, rp, target.get_parents())
ancestors = set.intersection(lp, rp)
if len(ancestors) == 0:
return {}
comb = list()
temp = set(ancestors)
single_table = {x.name: True for x in ancestors}
while len(temp) != 0:
ans = temp.pop()
for a in temp:
if set.intersection(ans.get_children(), a.get_children(),
ancestors) != 0:
if not ans.is_descendent_of(
a, level * 2) and not a.is_descendent_of(ans):
comb.append({ans, a})
single_table[ans.name] = False
single_table[a.name] = False
if single_table[ans.name]:
comb.append({ans})
border = set()
score = 0
raw_score = 0
for x in comb:
destination = set(x)
temp_boarder = {target}
while len(destination) != 0:
for tb in set(temp_boarder):
if tb in destination:
to_remove = True
for tb2 in temp_boarder:
if tb2.is_descendent_of(tb, level * 2):
to_remove = False
break
if to_remove:
destination.remove(tb)
continue
for d in destination:
if tb.is_descendent_of(d, level * 2):
temp_boarder.remove(tb)
temp_boarder.update(tb.get_parents())
break
clean_boarder = set()
for t in temp_boarder:
if not isinstance(t, Constant):
clean_boarder.add(t)
if len(clean_boarder) <= 3:
evaluator = set()
for eva in total:
if eva in evaluator:
continue
for tb in temp_boarder:
if eva.is_descendent_of(tb, level * 2):
if maj_mod.get_net(
eva.name) is None and eva.name not in skipped:
evaluator.add(eva)
break
if len(evaluator) - sum(b.name in skipped
for b in temp_boarder) > score:
border = temp_boarder
score = len(evaluator) - sum(b.name in skipped
for b in temp_boarder)
raw_score = len(evaluator)
continue
if len(evaluator) - sum(b.name in skipped
for b in temp_boarder) == score:
# print(target.name, len(evaluator), score, raw_score, [x.name for x in border], [x.name for x in temp_boarder])
if len(border) == 0:
border = temp_boarder
score = len(evaluator) - sum(b.name in skipped
for b in temp_boarder)
raw_score = len(evaluator)
else:
if len(evaluator) > raw_score:
border = temp_boarder
score = len(evaluator) - sum(b.name in skipped
for b in temp_boarder)
raw_score = len(evaluator)
if len(border) != 3:
return {}
for t in total:
for b in border:
if t.is_descendent_of(b, level * 2):
skipped.add(t.name)
break
return border
def majority_mapping(lib: Library, mod: Module):
for mb in majority_blocks.keys():
border = [mod.get_net(x.name) for x in majority_blocks[mb][0]]
selection = majority_blocks[mb][1]
internal_nets = dict()
for candidate in set.union(*[b.get_children() for b in border]):
bdn = set(x.name for x in candidate.get_parents())
mutual = set.intersection(
set(x.name for x in candidate.get_parents()),
set(b.name for b in border))
if mutual == bdn:
if candidate.name not in majority_blocks.keys():
candidate_inputs = [
BooleanVariable(x.connection.name)
for x in candidate.source_instance.input_pins
]
candidate_truth = candidate.source_instance.truth_value()
candidate_boolean = BooleanNode(candidate.name)
candidate_boolean.assign(candidate_inputs, candidate_truth)
candidate_boolean.reorder([b.name for b in border])
pos = [[b.name for b in border].index(x.name)
for x in candidate_boolean.inputs]
for i in range(40):
if majority_primary_truth[
i] == candidate_boolean.truth_value and majority_primary_inputs[
i] == pos:
internal_nets[i] = candidate
break
min_selection = None
final_selection = None
for s in selection:
temp = set.union(set(int(x / 2) for x in internal_nets.keys()),
set(int(x / 2) for x in s))
if min_selection is None:
min_selection = temp
final_selection = s
else:
if len(temp) < len(min_selection):
min_selection = temp
final_selection = s
continue
if len(temp) == len(min_selection):
if sum(x > 3 for x in temp) < sum(x > 3
for x in min_selection):
min_selection = temp
final_selection = s
final = list()
pre_wires = list()
for c in final_selection:
if internal_nets.get(c) is None:
if c % 2 == 1:
counter = c - 1
else:
counter = c + 1
if internal_nets.get(counter) is None:
pre_wires.append(None)
final.append(True)
else:
pre_wires.append(internal_nets.get(counter))
final.append(False)
else:
pre_wires.append(internal_nets.get(c))
final.append(True)
majority_mapping_single(lib, mod, mod.get_net(mb), border,
final_selection, pre_wires, final)
