def Simulate(self, tb_config, tst_data, dut_params={}, verbose=False):
_start = time.time()
tb = self.Testbench(tb_config, tst_data, dut_params, verbose)
# tb = traceSignals(self.Testbench, tb_config, tst_data, dut_params, verbose)
Simulation(tb).run()
if verbose:
mylog.infob("Simulation took %s seconds" % (time.time() - _start))
def convert(self, hdl='verilog', params={}, verbose=True):
'''|
| Converts convertible to HDL
|________'''
if self.IMPL == self.BEH:
mylog.err("Behavior models can not be converted to verilog!")
exit(0)
self.is_top = True
# Add resets, clock and overwritten parameters to top interface
top_kwargs = {}
top_kwargs.update(self.get_all_clocks())
top_kwargs.update(self.get_all_resets())
top_kwargs.update(self.get_all_parameters(params, verbose))
str_params = ''
for parameter, value in self.get_all_parameters(params, verbose).iteritems():
str_params += parameter + ' = ' + str(value) + ', '
if verbose and str_params != '':
mylog.infob('Parameters: {}'.format(str_params[:-2]))
# Add flatten interface signals to top interface
for x in self.get_all_interfaces().itervalues():
top_kwargs.update(x.get_all_signals())
if verbose:
mylog.infob('Converting to {}...'.format(hdl))
if hdl.lower()=='verilog':
toVerilog.name = self.get_name() + self.top_suffix
toVerilog(self.top, **top_kwargs)
elif hdl.lower()=='vhdl':
toVHDL.name = self.get_name() + self.top_suffix
toVHDL(self.top, **top_kwargs)
else:
raise ValueError("Unknown HDL: {}".format(hdl))
def Testbench(self, tb_config, tst_data, dut_params={}, verbose=False):
'''|
| Set-up and run a simulation of a HW module
| Uses a DutFactory
|________'''
self.is_top = True
# TODO: Dirty patches
BUS_PATCH = None
RST_PATCH = None
CLK_PATCH = None
trace = tb_config["trace"]
cosimulation = tb_config["cosimulation"]
sim_time = tb_config["simulation_time"]
self.ipgi = tb_config["ipgi"]
self.ipgo = tb_config["ipgo"]
self.fdump = tb_config["fdump"]
# Used to create test-vector files from behavior top-level model
FDUMP = self.fdump and self.IMPL == self.BEH
if len([self.get_interfaces()]) == 0:
mylog.infob("Nothing to simulate: module contains no interfaces!")
return
# Get clocks and instantiate clock generators
CLK_Period_ns = 1 # clk period = 20ns
clocks = self.get_all_clocks()
clk_gen = [clk.gen(CLK_Period_ns) for clk in clocks.values()]
CLK_PATCH = clocks.values()[-1] # TODO: Dirty patch, keeps the last from the list
# Get resets and instantiate reset generators
resets = self.get_all_resets()
rst_gen = [rst.pulse(CLK_PATCH, 10) for rst in resets.values()]
RST_PATCH = resets.values()[-1] # TODO: Dirty patch, keeps the last from the list
# Get interfaces
interfaces = self.get_all_interfaces(FDUMP)
# Overwrite default parameters
parameters = self.get_all_parameters(overwrite_params=dut_params, verbose=True)
# Add resets, clock, interfaces, and parameter to DUT argument dictionary
dut_kwargs = {}
dut_kwargs.update(resets)
dut_kwargs.update(clocks)
dut_kwargs.update(interfaces)
dut_kwargs.update(parameters)
## Create DUT factory
#dutFact = DutFactory()
## Configure DUT factory
#if cosimulation:
#dutFact.selectSimulator('icarus')
#else:
#dutFact.selectSimulator('myhdl')
#if trace:
#dutFact.enableTrace()
# Generate DUT
#sim_dut = dutFact(self, **dut_kwargs)
sim_dut = DutFactory(cosimulation, trace).getDut(self, **dut_kwargs)
sim_control = self.simulationControl(tst_data=tst_data, sim_time=sim_time, **dut_kwargs)
return instances()
