def setUpClass(self):
self.dio = DigitalInputOutput(Bank.A, [DIOChannel.DIO0])
self.expectedRegisterValue = {
'channel3':
0b1111111111111111111111111111111111111111111111111111110000111111,
'channel16':
0b1111111111111111111111111100000011111111111111111111111111111111,
}
class Test_SPI(unittest.TestCase):
@classmethod
def setUpClass(self):
self.cs = DigitalInputOutput(bank, [cs_channel])
self.spi = SPI(frequency, bank, clock_phase, clock_polarity,
data_direction, frame_length)
@classmethod
def tearDownClass(self):
self.spi.close()
self.cs.close()
def __writeAndRead(self):
self.cs.write(False, [cs_channel])
self.spi.write([0x80])
value_array = self.spi.read(1)
self.cs.write(True, [cs_channel])
return value_array
def __writeread(self):
self.cs.write(False, [cs_channel])
value_array = self.spi.writeread([0x80])
self.cs.write(True, [cs_channel])
return value_array
def test_WriteAndRead_ReturnExpectedReadback(self):
value_array = self.__writeAndRead()
self.assertEqual(value_array[0], 'e5')
def test_WriteRead_ReturnExpectedReadback(self):
value_array = self.__writeread()
self.assertEqual(value_array[0], 'e5')
class Test_DigitalInputOuput_Assertion(unittest.TestCase):
@classmethod
def setUpClass(self):
self.value = True
self.channel = [DIOChannel.DIO1]
self.dio = DigitalInputOutput(bank,
[DIOChannel.DIO2, DIOChannel.DIO3, DIOChannel.DIO4, DIOChannel.DIO8,
DIOChannel.DIO9, DIOChannel.DIO10, DIOChannel.DIO11, DIOChannel.DIO12])
@classmethod
def tearDownClass(self):
self.dio.close()
def test_writeInvalidValue_ShowAssertion(self):
with self.assertRaises(AssertionError):
self.dio.write(200, self.channel)
def test_writeInvalidChannel_ShowAssertion(self):
with self.assertRaises(AssertionError):
self.dio.write(self.value, [20])
def test_readInvalidChannel_ShowAssertion(self):
with self.assertRaises(AssertionError):
self.dio.read([20])
class Test_SysSelect64BitCalculation(unittest.TestCase):
@classmethod
def setUpClass(self):
self.dio = DigitalInputOutput(Bank.A, [DIOChannel.DIO0])
self.expectedRegisterValue = {
'channel3':
0b1111111111111111111111111111111111111111111111111111110000111111,
'channel16':
0b1111111111111111111111111100000011111111111111111111111111111111,
}
@classmethod
def tearDownClass(self):
self.dio.close()
def test_ClearChannel3With0xFFFFFFFFFFFFFFFF_ReturnExpectedValue(self):
expectedRegisterValue = self.expectedRegisterValue['channel3']
result = self.dio.clear_sys_select(0xFFFFFFFFFFFFFFFF, channel3,
number_of_channels_to_write_2)
self.assertEqual(result, expectedRegisterValue)
def test_SetChannel3With0xFFFFFFFFFFFFFFFF_ReturnExpectedValue(self):
expectedRegisterValue = 0b1111111111111111111111111111111111111111111111111111110101111111
result = self.dio.set_sys_select(
self.expectedRegisterValue['channel3'], channel3,
number_of_channels_to_write_2, '01')
self.assertEqual(result, expectedRegisterValue)
def test_ClearChannel16With0xFFFFFFFFFFFFFFFF_ReturnExpectedValue(self):
expectedRegisterValue = self.expectedRegisterValue['channel16']
result = self.dio.clear_sys_select(0xFFFFFFFFFFFFFFFF, channel16,
number_of_channels_to_write_3)
self.assertEqual(result, expectedRegisterValue)
def test_SetChannel16With0xFFFFFFFFFFFFFFFF_ReturnExpectedValue(self):
expectedRegisterValue = 0b1111111111111111111111111110101011111111111111111111111111111111
result = self.dio.set_sys_select(
self.expectedRegisterValue['channel16'], channel16,
number_of_channels_to_write_3, '10')
self.assertEqual(result, expectedRegisterValue)
def setUpClass(self):
self.cs = DigitalInputOutput(bank, [cs_channel])
self.spi = SPI(frequency, bank, clock_phase, clock_polarity,
data_direction, frame_length)
Hardware setup:
1. Connect DIO2 to DIO4 on bank A.
2. Connect DIO3 to DIO8 on bank A.
Result:
The program writes values to DIO2 and DIO3 and reads back values from DIO4
and DIO8 on bank A.
"""
import time
from nielvis import DigitalInputOutput, Bank, DIOChannel
# specify the bank
bank = Bank.A
# specify the DIO channels
channel2 = DIOChannel.DIO2
channel3 = DIOChannel.DIO3
channel4 = DIOChannel.DIO4
channel8 = DIOChannel.DIO8
# configure a DIO session
with DigitalInputOutput(bank, [channel2, channel3, channel4, channel8]) as DIO:
# define the value as a Boolean
value = False
# write the value False to both DIO2 and DIO3 on bank A
# the written value must be a Boolean variable
DIO.write(value, [channel2, channel3])
# read values from DIO4 and DIO8 on bank A
data = DIO.read([channel4, channel8])
# print the values read. The values read are [0,0]
print(data)
# specify the clock phase at which the data remains stable in the SPI
# transmission cycle
clock_phase = SPIClockPhase.TRAILING
# specify the base level of the clock signal and the logic level of the
# leading and trailing edges
clock_polarity = SPIClockPolarity.HIGH
# specify the order in which the bits in the SPI frame are transmitted
data_direction = SPIDataDirection.MSB
# specify the number of bits that make up one SPI transmission frame
frame_length = 8
# specify the chip select channel, the DIO channel should be low when writing
# or reading data
cs_channel = DIOChannel.DIO0
# configure the chip select channel
cs = DigitalInputOutput(bank, [cs_channel])
##############################################################################
# Section 1:
# You use the write function and the read function to write to and read from
# the SPI channel.
##############################################################################
# configure an SPI session
with SPI(frequency, bank, clock_phase, clock_polarity, data_direction,
frame_length) as spi:
# specify the bytes to write to the SPI channel
data_to_write = [0x80]
# set the chip select of SPI to low
cs.write(False, [cs_channel])
# write data to the SPI channel
Cg3 = DIOChannel.DIO2
Cg4 = DIOChannel.DIO3
Cg5 = DIOChannel.DIO4
Cg6 = DIOChannel.DIO5
Cg7 = DIOChannel.DIO6
Cg8 = DIOChannel.DIO7
Cr1 = DIOChannel.DIO8
Cr2 = DIOChannel.DIO9
Cr3 = DIOChannel.DIO10
Cr4 = DIOChannel.DIO11
Cr5 = DIOChannel.DIO12
Cr6 = DIOChannel.DIO13
Cr7 = DIOChannel.DIO14
Cr8 = DIOChannel.DIO15
with DigitalInputOutput(bank_A, [R1, R2, R3, R4, R5, R6, R7, R8]) as DIO_A:
with DigitalInputOutput(bank_B, [
Cg1, Cg2, Cg3, Cg4, Cg5, Cg6, Cg7, Cg8, Cr1, Cr2, Cr3, Cr4, Cr5,
Cr6, Cr7, Cr8
]) as DIO_B:
while True:
value1 = False
value2 = True
#初始状态：R1-R8=H Cg1-Cg8=L
DIO_A.write(value2, [R1, R2, R3, R4, R5, R6, R7, R8])
DIO_B.write(value1, [
Cg1, Cg2, Cg3, Cg4, Cg5, Cg6, Cg7, Cg8, Cr1, Cr2, Cr3, Cr4,
Cr5, Cr6, Cr7, Cr8
])
#所有的黄灯亮
def setUpClass(self):
self.value = True
self.channel = [DIOChannel.DIO1]
self.dio = DigitalInputOutput(bank,
[DIOChannel.DIO2, DIOChannel.DIO3, DIOChannel.DIO4, DIOChannel.DIO8,
DIOChannel.DIO9, DIOChannel.DIO10, DIOChannel.DIO11, DIOChannel.DIO12])
class Test_DigitalInputOuput(unittest.TestCase):
@classmethod
def setUpClass(self):
self.value = True
self.dio = DigitalInputOutput(bank,
[DIOChannel.DIO2, DIOChannel.DIO3, DIOChannel.DIO4, DIOChannel.DIO8,
DIOChannel.DIO9, DIOChannel.DIO10, DIOChannel.DIO11, DIOChannel.DIO12])
@classmethod
def tearDownClass(self):
self.dio.close()
def test_WriteAndReadFourChannels(self):
self.dio.write(self.value, [DIOChannel.DIO2, DIOChannel.DIO3, DIOChannel.DIO4, DIOChannel.DIO8])
data = self.dio.read([DIOChannel.DIO9, DIOChannel.DIO10, DIOChannel.DIO11, DIOChannel.DIO12])
self.assertEqual(data, [1, 1, 1, 1])
def test_WriteAndReadTwoChannels(self):
self.dio.write(self.value, [DIOChannel.DIO2, DIOChannel.DIO4])
data = self.dio.read([DIOChannel.DIO9, DIOChannel.DIO11])
self.assertEqual(data, [1, 1])
def test_WriteAndReadSingleChannel(self):
self.dio.write(not self.value, [DIOChannel.DIO3])
data = self.dio.read([DIOChannel.DIO10])
self.assertEqual(data, [0])
ok = True
eyes = False
if 'left' in command['which']:
lights.append(left)
eyes = True
msg += "(Left)"
if 'right' in command['which']:
lights.append(right)
eyes = True
msg += "(Right)"
if 'bottom' in command['which']:
lights.append(bottom)
eyes = True
msg += "(Bottom)"
if not eyes:
msg += "(NoEyes)"
DIO.write(True, lights)
time.sleep(duration)
DIO.write(False, [left, right, bottom])
reply = {"result": ok, "message": msg}
await websocket.send(json.dumps(reply))
except Exception as e:
print(e)
if __name__ == "__main__":
# configure a DIO session
with DigitalInputOutput(bank, [left, right, bottom]) as DIO:
asyncio.get_event_loop().run_until_complete(listen(DIO))
from nielvis import DigitalInputOutput, Bank, DIOChannel, Button
# specify the bank
bank = Bank.A
# specify the DIO channels
channel0 = DIOChannel.DIO3
channel1 = DIOChannel.DIO2
channel2 = DIOChannel.DIO1
channel3 = DIOChannel.DIO0
channel4 = DIOChannel.DIO7
channel5 = DIOChannel.DIO6
channel6 = DIOChannel.DIO5
channel7 = DIOChannel.DIO4
# configure a DIO session
with DigitalInputOutput(bank, [
channel0, channel1, channel2, channel3, channel4, channel5, channel6,
channel7
]) as DIO:
# define the value as a Boolean
value = False
#循环扫描valumn1-valumn4
while True:
data_out1 = 'x'
data_out2 = ' '
for num in range(0, 4):
data = [1, 1, 1, 1]
if num == 0:
DIO.write(value, [channel0]) #valumn1置为FALSE扫描第一列
data = DIO.read([channel4, channel5, channel6,
channel7]) #将第一列写入data中，触发按键为0，未触发为1
if data[0] == 0:
data_out1 = '1'
# leading and trailing edges
clock_polarity = SPIClockPolarity.HIGH
# specify the order in which the bits in the SPI frame are transmitted
data_direction = SPIDataDirection. MSB
# specify the number of bits that make up one SPI transmission frame
frame_length = 8
# specify the chip select channel, the DIO channel should be low when writing
# or reading data
cs_channel = DIOChannel.DIO0
MISO_channel = DIOChannel.DIO6
wp_channel = DIOChannel.DIO1
MOSI_channel = DIOChannel.DIO7
sck_channel = DIOChannel.DIO5
# configure the chip select channel
cs = DigitalInputOutput(bank, [cs_channel])
MISO = DigitalInputOutput(bank, [MISO_channel])
MOSI = DigitalInputOutput(bank, [MOSI_channel])
sck = DigitalInputOutput(bank, [sck_channel])
with SPI(frequency,
bank,
clock_phase,
clock_polarity,
data_direction,
frame_length) as spi:
########################################specify the bytes to write to the SPI channel####################################
#cmod_wren: Set the write enable latch
comd_wren = [0b00000110]
#write commond: writing the data to address 000000000
comd_write = [0b00000010]
def setUpClass(self):
self.dio = DigitalInputOutput(Bank.A, [DIOChannel.DIO0])
self.expectedRegisterValue = {
'0xAAAAAAAA': 0b10101010101010101010100000101010,
'0xFFFFFFFF': 0b11111111111111111111110000111111,
}
