class Test_DigitalInputOuput(unittest.TestCase): @classmethod def setUpClass(self): self.value = True self.dio = DigitalInputOutput(bank, [DIOChannel.DIO2, DIOChannel.DIO3, DIOChannel.DIO4, DIOChannel.DIO8, DIOChannel.DIO9, DIOChannel.DIO10, DIOChannel.DIO11, DIOChannel.DIO12]) @classmethod def tearDownClass(self): self.dio.close() def test_WriteAndReadFourChannels(self): self.dio.write(self.value, [DIOChannel.DIO2, DIOChannel.DIO3, DIOChannel.DIO4, DIOChannel.DIO8]) data = self.dio.read([DIOChannel.DIO9, DIOChannel.DIO10, DIOChannel.DIO11, DIOChannel.DIO12]) self.assertEqual(data, [1, 1, 1, 1]) def test_WriteAndReadTwoChannels(self): self.dio.write(self.value, [DIOChannel.DIO2, DIOChannel.DIO4]) data = self.dio.read([DIOChannel.DIO9, DIOChannel.DIO11]) self.assertEqual(data, [1, 1]) def test_WriteAndReadSingleChannel(self): self.dio.write(not self.value, [DIOChannel.DIO3]) data = self.dio.read([DIOChannel.DIO10]) self.assertEqual(data, [0])
class Test_SysSelect64BitCalculation(unittest.TestCase): @classmethod def setUpClass(self): self.dio = DigitalInputOutput(Bank.A, [DIOChannel.DIO0]) self.expectedRegisterValue = { 'channel3': 0b1111111111111111111111111111111111111111111111111111110000111111, 'channel16': 0b1111111111111111111111111100000011111111111111111111111111111111, } @classmethod def tearDownClass(self): self.dio.close() def test_ClearChannel3With0xFFFFFFFFFFFFFFFF_ReturnExpectedValue(self): expectedRegisterValue = self.expectedRegisterValue['channel3'] result = self.dio.clear_sys_select(0xFFFFFFFFFFFFFFFF, channel3, number_of_channels_to_write_2) self.assertEqual(result, expectedRegisterValue) def test_SetChannel3With0xFFFFFFFFFFFFFFFF_ReturnExpectedValue(self): expectedRegisterValue = 0b1111111111111111111111111111111111111111111111111111110101111111 result = self.dio.set_sys_select( self.expectedRegisterValue['channel3'], channel3, number_of_channels_to_write_2, '01') self.assertEqual(result, expectedRegisterValue) def test_ClearChannel16With0xFFFFFFFFFFFFFFFF_ReturnExpectedValue(self): expectedRegisterValue = self.expectedRegisterValue['channel16'] result = self.dio.clear_sys_select(0xFFFFFFFFFFFFFFFF, channel16, number_of_channels_to_write_3) self.assertEqual(result, expectedRegisterValue) def test_SetChannel16With0xFFFFFFFFFFFFFFFF_ReturnExpectedValue(self): expectedRegisterValue = 0b1111111111111111111111111110101011111111111111111111111111111111 result = self.dio.set_sys_select( self.expectedRegisterValue['channel16'], channel16, number_of_channels_to_write_3, '10') self.assertEqual(result, expectedRegisterValue)
class Test_SPI(unittest.TestCase): @classmethod def setUpClass(self): self.cs = DigitalInputOutput(bank, [cs_channel]) self.spi = SPI(frequency, bank, clock_phase, clock_polarity, data_direction, frame_length) @classmethod def tearDownClass(self): self.spi.close() self.cs.close() def __writeAndRead(self): self.cs.write(False, [cs_channel]) self.spi.write([0x80]) value_array = self.spi.read(1) self.cs.write(True, [cs_channel]) return value_array def __writeread(self): self.cs.write(False, [cs_channel]) value_array = self.spi.writeread([0x80]) self.cs.write(True, [cs_channel]) return value_array def test_WriteAndRead_ReturnExpectedReadback(self): value_array = self.__writeAndRead() self.assertEqual(value_array[0], 'e5') def test_WriteRead_ReturnExpectedReadback(self): value_array = self.__writeread() self.assertEqual(value_array[0], 'e5')
class Test_DigitalInputOuput_Assertion(unittest.TestCase): @classmethod def setUpClass(self): self.value = True self.channel = [DIOChannel.DIO1] self.dio = DigitalInputOutput(bank, [DIOChannel.DIO2, DIOChannel.DIO3, DIOChannel.DIO4, DIOChannel.DIO8, DIOChannel.DIO9, DIOChannel.DIO10, DIOChannel.DIO11, DIOChannel.DIO12]) @classmethod def tearDownClass(self): self.dio.close() def test_writeInvalidValue_ShowAssertion(self): with self.assertRaises(AssertionError): self.dio.write(200, self.channel) def test_writeInvalidChannel_ShowAssertion(self): with self.assertRaises(AssertionError): self.dio.write(self.value, [20]) def test_readInvalidChannel_ShowAssertion(self): with self.assertRaises(AssertionError): self.dio.read([20])
cs.write(True, [cs_channel]) # print the data print("value read from SPI.read: ", value_array[0]) ############################################################################## # Section 2: # You use the writeread function which reads back a value immediately after it # is written. ############################################################################## # specify the number of bits that make up one SPI transmission frame frame_length = 16 # configure an SPI session with SPI(frequency, bank, clock_phase, clock_polarity, data_direction, frame_length) as spi: # specify the bytes to write to the SPI channel, need a 16-bit value # because frame_length is 16 data_to_write = [0x8000] # set the chip select of SPI to low cs.write(False, [cs_channel]) # write to and read from the SPI channel value_array = spi.writeread(data_to_write) # set the chip select of SPI high after writing/reading cs.write(True, [cs_channel]) # print the data print("value read from SPI.writeread: ", value_array[0]) # close the channel cs.close()