def main():
segmk = Segmaker("design.bits")
segmk.set_def_bt('BLOCK_RAM')
print("Loading tags")
'''
'''
with open('params.json') as f:
params = json.load(f)
for param in params:
for initp in range(NUM_INITP_PARAMS):
p = 'INITP_{:02X}'.format(initp)
val = param[p]
for bit in range(BITS_PER_PARAM):
segmk.add_site_tag(
param['site'], "{p}[{bit:03d}]".format(
p=p,
bit=bit,
), val & (1 << bit) != 0)
for init in range(NUM_INIT_PARAMS):
p = 'INIT_{:02X}'.format(init)
val = param[p]
for bit in range(BITS_PER_PARAM):
segmk.add_site_tag(
param['site'], "{p}[{bit:03d}]".format(
p=p,
bit=bit,
), val & (1 << bit) != 0)
segmk.compile()
segmk.write()
def main():
segmk = Segmaker("design.bits")
fuz_dir = os.getenv("FUZDIR", None)
assert fuz_dir
with open(os.path.join(fuz_dir, "attrs.json"), "r") as attr_file:
attrs = json.load(attr_file)
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
site = params['site']
for param, param_info in attrs.items():
value = params[param]
param_type = param_info["type"]
param_digits = param_info["digits"]
param_values = param_info["values"]
if param_type == BIN:
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=value, digits=param_digits)[::-1]
]
for i in range(param_digits):
segmk.add_site_tag(site, "%s[%u]" % (param, i), bitstr[i])
else:
assert param_type == BOOL
segmk.add_site_tag(site, param, value == "TRUE")
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
site = params['site']
for param, _ in boolean_params:
value = params[param]
segmk.add_site_tag(site, param, value)
for param, digits in hex_params + int_params:
value = int(params[param])
bitstr = [
int(x)
for x in "{value:0{digits}b}".format(value=value,
digits=digits)[::-1]
]
for i in range(digits):
segmk.add_site_tag(site, '%s[%u]' % (param, i), bitstr[i])
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
for row in params:
base_name = 'BUFHCE_X{}Y{}'.format(row['x'], row['y'])
segmk.add_site_tag(row['site'], '{}.IN_USE'.format(base_name),
row['IN_USE'])
if not row['IN_USE']:
continue
segmk.add_site_tag(row['site'], '{}.INIT_OUT'.format(base_name),
row['INIT_OUT'])
segmk.add_site_tag(row['site'], '{}.ZINV_CE'.format(base_name),
1 ^ row['IS_CE_INVERTED'])
# SYNC is a zero pattern
for opt in ['ASYNC']:
segmk.add_site_tag(row['site'],
'{}.CE_TYPE.'.format(base_name) + opt,
verilog.unquote(row['CE_TYPE']) == opt)
segmk.compile()
segmk.write()
def main():
segmk = Segmaker("design.bits")
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
for row in params:
base_name = 'BUFGCTRL_X{}Y{}'.format(row['x'], row['y'])
segmk.add_site_tag(row['site'], '{}.IN_USE'.format(base_name),
row['IN_USE'])
if not row['IN_USE']:
continue
for param in (
'INIT_OUT',
'IS_IGNORE0_INVERTED',
'IS_IGNORE1_INVERTED',
):
segmk.add_site_tag(row['site'], '{}.{}'.format(base_name, param),
row[param])
for param in ('PRESELECT_I0', ):
segmk.add_site_tag(row['site'], '{}.Z{}'.format(base_name, param),
1 ^ row[param])
for param in ('PRESELECT_I1', ):
segmk.add_site_tag(row['site'], '{}.{}'.format(base_name, param),
row[param])
for param, tag in (('IS_CE0_INVERTED', 'ZINV_CE0'), ('IS_S0_INVERTED',
'ZINV_S0'),
('IS_CE1_INVERTED', 'ZINV_CE1'), ('IS_S1_INVERTED',
'ZINV_S1')):
segmk.add_site_tag(row['site'], '{}.{}'.format(base_name, tag),
1 ^ row[param])
segmk.compile(bitfilter=bitfilter)
segmk.write()
def run():
segmk = Segmaker("design.bits")
clk_inverts = {}
with open('design.csv', 'r') as f:
for params in csv.DictReader(f):
clk_inverts[params['site']] = params
print("Loading tags")
f = open('params.jl', 'r')
f.readline()
for l in f:
j = json.loads(l)
ps = j['params']
assert j['module'] == 'my_RAMB18E1'
site = verilog.unquote(ps['LOC'])
bus_tags(segmk, ps, site)
if ps['RAM_MODE'] == '"TDP"':
rw_width_tags(segmk, ps, site)
segmk.add_site_tag(
site, 'SDP_READ_WIDTH_36', ps['RAM_MODE'] == '"SDP"'
and int(ps['READ_WIDTH_A']) == 36)
segmk.add_site_tag(
site, 'SDP_WRITE_WIDTH_36', ps['RAM_MODE'] == '"SDP"'
and int(ps['WRITE_WIDTH_B']) == 36)
if ps['READ_WIDTH_A'] < 36 and ps['WRITE_WIDTH_B'] < 36:
isinv_tags(segmk, ps, site, clk_inverts[site])
write_mode_tags(segmk, ps, site)
write_rstreg_priority(segmk, ps, site)
write_rdaddr_collision(segmk, ps, site)
def bitfilter(frame, bit):
# rw_width_tags() aliasing interconnect on large widths
return frame not in (0, 20, 21)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
for tile_param in params:
if tile_param['BRAM36_IN_USE']:
write_ram_ext_tags(segmk, tile_param)
segmk.add_site_tag(tile_param['site'], 'EN_ECC_READ',
tile_param['EN_ECC_READ'])
segmk.add_site_tag(tile_param['site'], 'EN_ECC_WRITE',
tile_param['EN_ECC_WRITE'])
for ab in 'ab':
for rw in 'rw':
if rw == 'r':
dir = 'READ'
else:
dir = 'WRITE'
width = tile_param['bram36_{}{}_width'.format(rw, ab)]
tag = 'BRAM36_{}_WIDTH_{}_1'.format(dir, ab.upper())
if width == 1:
segmk.add_site_tag(tile_param['site'], tag,
tile_param['BRAM36_IN_USE'])
segmk.compile()
segmk.write()
def main():
segmk = Segmaker("design.bits")
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
for tile_param in params:
if tile_param['BRAM36_IN_USE']:
write_ram_ext_tags(segmk, tile_param)
segmk.add_site_tag(tile_param['site'], 'BRAM36_IN_USE', 1)
segmk.add_site_tag(tile_param['site'], 'EN_ECC_READ',
tile_param['EN_ECC_READ'])
segmk.add_site_tag(tile_param['site'], 'EN_ECC_WRITE',
tile_param['EN_ECC_WRITE'])
else:
segmk.add_site_tag(tile_param['site'], 'BRAM36_IN_USE', 0)
segmk.compile()
segmk.write()
def run():
segmk = Segmaker("design.bits")
print("Loading tags")
f = open('params.jl', 'r')
design = json.load(f)
for p in design:
ps = p["params"]
if p["site_type"] in "ICAP":
param = verilog.unquote(ps["ICAP_WIDTH"])
segmaker.add_site_group_zero(segmk, p["site"], "ICAP_WIDTH_",
["X32", "X8", "X16"], "X32", param)
elif p["site_type"] in "BSCAN":
param = str(ps["JTAG_CHAIN"])
segmaker.add_site_group_zero(segmk, p["site"], "JTAG_CHAIN_",
["1", "2", "3", "4"], param, param)
elif p["site_type"] in "CAPTURE":
param = verilog.unquote(ps["ONESHOT"])
segmk.add_site_tag(p["site"], "ONESHOT",
True if param in "TRUE" else False)
elif p["site_type"] in "STARTUP":
param = verilog.unquote(ps["PROG_USR"])
segmk.add_site_tag(p["site"], "PROG_USR",
True if param in "TRUE" else False)
elif p["site_type"] in "FRAME_ECC":
param = verilog.unquote(ps["FARSRC"])
segmaker.add_site_group_zero(segmk, p["site"], "FARSRC_",
["FAR", "EFAR"], param, param)
elif p["site_type"] in ["USR_ACCESS", "DCIRESET"]:
feature = "ENABLED"
segmk.add_site_tag(p["site"], feature,
True if ps["ENABLED"] else False)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
# Create map of iobank -> sites
iobanks = {}
site_to_iobank = {}
iobank_iostandards = {}
with open(os.path.join(os.getenv('FUZDIR'), 'build', 'iobanks.txt')) as f:
for l in f:
iob_site, iobank = l.strip().split(',')
iobank = int(iobank)
if iobank not in iobanks:
iobanks[iobank] = set()
iobanks[iobank].add(iob_site)
assert iob_site not in site_to_iobank
site_to_iobank[iob_site] = iobank
for iobank in iobanks:
iobank_iostandards[iobank] = set()
# Load a list of PUDC_B pin function tiles. They are configured differently
# by the vendor tools so need to be skipped
pudc_tiles = set()
with open(os.path.join(os.getenv('FUZDIR'), 'build',
'pudc_sites.csv')) as f:
for l in csv.DictReader(f):
pudc_tiles.add(l["tile"])
print("Loading tags")
segmk = Segmaker("design.bits")
'''
port,site,tile,pin,slew,drive,pulltype
di[0],IOB_X0Y107,LIOB33_X0Y107,A21,PULLDOWN
di[10],IOB_X0Y147,LIOB33_X0Y147,F14,PULLUP
'''
with open('params.json', 'r') as f:
design = json.load(f)
diff_pairs = set()
for d in design['tiles']:
iostandard = verilog.unquote(d['IOSTANDARD'])
if iostandard.startswith('DIFF_'):
diff_pairs.add(d['pair_site'])
for d in design['tiles']:
site = d['site']
if d['tile'] in pudc_tiles:
continue
if site in diff_pairs:
continue
iostandard = verilog.unquote(d['IOSTANDARD'])
if iostandard.startswith('DIFF_'):
iostandard = iostandard[5:]
iobank_iostandards[site_to_iobank[site]].add(iostandard)
segmk.add_site_tag(site,
'_'.join(STEPDOWN_IOSTANDARDS) + '.STEPDOWN',
iostandard in STEPDOWN_IOSTANDARDS)
if 'IN_TERM' in d:
segmaker.add_site_group_zero(segmk, site, 'IN_TERM.', [
'NONE', 'UNTUNED_SPLIT_40', 'UNTUNED_SPLIT_50',
'UNTUNED_SPLIT_60'
], 'NONE', d['IN_TERM'])
if d['type'] is None:
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.IN_ONLY'.format(iostandard), 0)
elif d['type'] == 'IBUF':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN_DIFF'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.IN_ONLY'.format(iostandard), 1)
segmk.add_tile_tag(d['tile'], 'IN_DIFF', 0)
if iostandard in IBUF_LOW_PWR_SUPPORTED:
segmk.add_site_tag(site, 'IBUF_LOW_PWR', d['IBUF_LOW_PWR'])
segmk.add_site_tag(site, 'ZIBUF_LOW_PWR',
1 ^ d['IBUF_LOW_PWR'])
elif d['type'] == 'IBUFDS':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN_DIFF'.format(iostandard), 1)
segmk.add_site_tag(d['pair_site'],
'{}.IN_DIFF'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.IN_ONLY'.format(iostandard), 1)
segmk.add_tile_tag(d['tile'], 'IN_DIFF', 1)
elif d['type'] == 'OBUF':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
segmk.add_tile_tag(d['tile'], 'OUT_DIFF', 0)
elif d['type'] == 'OBUFDS':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
segmk.add_tile_tag(d['tile'], 'OUT_DIFF', 1)
segmk.add_tile_tag(d['tile'], 'OUT_TDIFF', 0)
elif d['type'] == 'OBUFTDS':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
segmk.add_tile_tag(d['tile'], 'OUT_DIFF', 1)
segmk.add_tile_tag(d['tile'], 'OUT_TDIFF', 1)
elif d['type'] == 'IOBUF_INTERMDISABLE':
segmk.add_site_tag(site, 'INOUT', 1)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
if d['type'] is not None:
segmaker.add_site_group_zero(
segmk, site, "PULLTYPE.",
("NONE", "KEEPER", "PULLDOWN", "PULLUP"), "PULLDOWN",
verilog.unquote(d['PULLTYPE']))
if d['type'] in [None, 'IBUF', 'IBUFDS']:
continue
drive_opts = set()
for opt in ("LVCMOS25", "LVCMOS33", "LVCMOS18", "LVCMOS15",
"LVCMOS12", 'LVTTL'):
for drive_opt in ("4", "8", "12", "16", "24"):
if drive_opt == "16" and opt == "LVCMOS12":
continue
if drive_opt == "24" and opt not in ["LVCMOS18", 'LVTTL']:
continue
drive_opts.add(mk_drive_opt(opt, drive_opt))
drive_opts.add(mk_drive_opt("SSTL135", None))
segmaker.add_site_group_zero(segmk, site, '', drive_opts,
mk_drive_opt('LVCMOS25', '12'),
mk_drive_opt(iostandard, d['DRIVE']))
for opt in ["SLOW", "FAST"]:
segmk.add_site_tag(site, iostandard + ".SLEW." + opt,
opt == verilog.unquote(d['SLEW']))
if 'ibufdisable_wire' in d:
segmk.add_site_tag(site, 'IBUFDISABLE.I',
d['ibufdisable_wire'] != '0')
if 'intermdisable_wire' in d:
segmk.add_site_tag(site, 'INTERMDISABLE.I',
d['intermdisable_wire'] != '0')
site_to_cmt = {}
site_to_tile = {}
tile_to_cmt = {}
cmt_to_idelay = {}
with open(os.path.join(os.getenv('FUZDIR'), 'build',
'cmt_regions.csv')) as f:
for l in f:
site, tile, cmt = l.strip().split(',')
site_to_tile[site] = tile
site_to_cmt[site] = cmt
tile_to_cmt[tile] = cmt
# Given IDELAYCTRL's are only located in HCLK_IOI3 tiles, and
# there is only on HCLK_IOI3 tile per CMT, update
# CMT -> IDELAYCTRL / tile map.
if 'IDELAYCTRL' in site:
assert cmt not in cmt_to_idelay
cmt_to_idelay[cmt] = site, tile
# For each IOBANK with an active VREF set the feature
cmt_vref_active = set()
with open('iobank_vref.csv') as f:
for l in f:
iobank, vref = l.strip().split(',')
iobank = int(iobank)
cmt = None
for cmt_site in iobanks[iobank]:
if cmt_site in site_to_cmt:
cmt = site_to_cmt[cmt_site]
break
if cmt is None:
continue
cmt_vref_active.add(cmt)
_, hclk_cmt_tile = cmt_to_idelay[cmt]
opt = 'VREF.V_{:d}_MV'.format(int(float(vref) * 1000))
segmk.add_tile_tag(hclk_cmt_tile, opt, 1)
for iobank in iobank_iostandards:
if len(iobank_iostandards[iobank]) == 0:
continue
for cmt_site in iobanks[iobank]:
if cmt_site in site_to_cmt:
cmt = site_to_cmt[cmt_site]
break
if cmt is None:
continue
_, hclk_cmt_tile = cmt_to_idelay[cmt]
assert len(iobank_iostandards[iobank]) == 1, iobank_iostandards[iobank]
iostandard = list(iobank_iostandards[iobank])[0]
segmk.add_tile_tag(hclk_cmt_tile, 'STEPDOWN', iostandard
in STEPDOWN_IOSTANDARDS)
# For IOBANK's with no active VREF, clear all VREF options.
for cmt, (_, hclk_cmt_tile) in cmt_to_idelay.items():
if cmt in cmt_vref_active:
continue
for vref in (
.600,
.675,
.75,
.90,
):
opt = 'VREF.V_{:d}_MV'.format(int(vref * 1000))
segmk.add_tile_tag(hclk_cmt_tile, opt, 0)
segmk.compile(bitfilter=bitfilter)
segmk.write(allow_empty=True)
# rewrite name of F78 source net: MUXes A and C have an F7 input, MUX B has an F8 input
if src == "F78":
if which in "AC":
src = "F7"
elif which == "B":
src = "F8"
else:
assert 0
# rewrite name of AX source net: It's actually AX, BX, CX, or DX
if src == "AX":
src = which + "X"
# add the 1-tag for this connection
tag = "%sFFMUX.%s" % (which, src)
segmk.add_site_tag(loc, tag, 1)
# remove this MUX from the cache, preventing generation of 0-tags for this MUX
cache[loc].remove(which)
# create 0-tags for all sources on the remaining (unused) MUXes
for loc, muxes in cache.items():
for which in muxes:
for src in "F7 F8 CY O5 AX XOR O6 MC31".split():
if src == "MC31" and which is not "D": continue
if src == "F7" and which not in "AC": continue
if src == "F8" and which not in "B": continue
if src == "AX": src = which + "X"
tag = "%sFFMUX.%s" % (which, src)
segmk.add_site_tag(loc, tag, 0)
#!/usr/bin/env python3
import sys, os, re
from prjxray.segmaker import Segmaker
segmk = Segmaker("design.bits")
print("Loading tags")
f = open('params.csv', 'r')
f.readline()
for l in f:
module, loc, loc2 = l.split(',')
# clb_PRECYINIT_AX => AX
src = module.replace('clb_PRECYINIT_', '')
'''
PRECYINIT
00_12 30_14 30_13
1 0 1 0
AX 1 0 0
CIN 0 0 1
0 0 0 0
'''
srcs = ('0', '1', 'AX', 'CIN')
for asrc in srcs:
segmk.add_site_tag(loc, "PRECYINIT.%s" % asrc, int(src == asrc))
segmk.compile()
segmk.write()
def run():
segmk = Segmaker("design.bits")
# Load tags
with open("params.json", "r") as fp:
data = json.load(fp)
loc_to_tile_site_map = {}
# Output tags
for param_list in data:
for params in param_list:
loc = verilog.unquote(params["SITE_LOC"])
get_xy = util.create_xy_fun('IOB_')
x, y = get_xy(loc.replace("ILOGIC", "IOB"))
loc_to_tile_site_map[loc] = params["TILE_NAME"] + ".IOB_Y%d" % (
y % 2)
# Site not used at all
if not params["IS_USED"]:
segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", 0)
segmk.add_site_tag(loc, "IDDR_OR_ISERDES.IN_USE", 0)
segmk.add_site_tag(loc, "ISERDES.IN_USE", 0)
segmk.add_site_tag(loc, "IDDR.IN_USE", 0)
segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0)
segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0)
for i in iface_types:
if i == "NETWORKING":
for j in data_rates:
for k in data_widths[j]:
tag = "ISERDES.%s.%s.W%s" % (i, j, k)
segmk.add_site_tag(loc, tag, 0)
else:
segmk.add_site_tag(loc, "ISERDES.%s.DDR.W4" % i, 0)
segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 0)
segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 0)
for i in range(1, 4 + 1):
segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, 0)
for i in range(1, 4 + 1):
segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0)
# segmk.add_site_tag(loc, "ISERDES.IS_CLKB_INVERTED", 0)
# segmk.add_site_tag(loc, "ISERDES.IS_CLK_INVERTED", 1)
segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", 0)
segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", 0)
segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0)
segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1)
segmk.add_site_tag(loc, "IDELMUXE3.P0", 0)
segmk.add_site_tag(loc, "IDELMUXE3.P1", 1)
segmk.add_site_tag(loc, "ISERDES.OFB_USED", 0)
# Site used as ISERDESE2
elif verilog.unquote(params["BEL_TYPE"]) == "ISERDESE2":
segmk.add_site_tag(loc, "IDDR_OR_ISERDES.IN_USE", 1)
segmk.add_site_tag(loc, "ISERDES.IN_USE", 1)
if "SHIFTOUT_USED" in params:
if params["CHAINED"]:
value = params["SHIFTOUT_USED"]
segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", value)
if "SERDES_MODE" in params:
value = verilog.unquote(params["SERDES_MODE"])
if value == "MASTER":
segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 1)
segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0)
if value == "SLAVE":
segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0)
segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 1)
iface_type = verilog.unquote(params["INTERFACE_TYPE"])
data_rate = verilog.unquote(params["DATA_RATE"])
data_width = int(params["DATA_WIDTH"])
for i in iface_types:
if i == "NETWORKING":
for j in data_rates:
for k in data_widths[j]:
tag = "ISERDES.%s.%s.W%s" % (i, j, k)
if i == iface_type:
if j == data_rate:
if k == data_width:
segmk.add_site_tag(loc, tag, 1)
else:
if i == iface_type:
segmk.add_site_tag(loc, "ISERDES.%s.DDR.W4" % i, 1)
if "NUM_CE" in params:
value = params["NUM_CE"]
if value == 1:
segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 1)
segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 0)
if value == 2:
segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 0)
segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 1)
for i in range(1, 4 + 1):
if ("INIT_Q%d" % i) in params:
segmk.add_site_tag(
loc, "IFF.ZINIT_Q%d" % i,
not params["INIT_Q%d" % i])
for i in range(1, 4 + 1):
if ("SRVAL_Q%d" % i) in params:
segmk.add_site_tag(
loc, "IFF.ZSRVAL_Q%d" % i,
not params["SRVAL_Q%d" % i])
for inv in ["CLK", "CLKB", "OCLK", "OCLKB", "CLKDIV",
"CLKDIVP"]:
if "IS_{}_INVERTED".format(inv) in params:
segmk.add_site_tag(
loc, "ISERDES.INV_{}".format(inv),
params["IS_{}_INVERTED".format(inv)])
segmk.add_site_tag(
loc, "ISERDES.ZINV_{}".format(inv),
not params["IS_{}_INVERTED".format(inv)])
if "DYN_CLKDIV_INV_EN" in params:
value = verilog.unquote(params["DYN_CLKDIV_INV_EN"])
segmk.add_site_tag(
loc, "ISERDES.DYN_CLKDIV_INV_EN", int(value == "TRUE"))
if "DYN_CLK_INV_EN" in params:
value = verilog.unquote(params["DYN_CLK_INV_EN"])
segmk.add_site_tag(
loc, "ISERDES.DYN_CLK_INV_EN", int(value == "TRUE"))
# This parameter actually controls muxes used both in ILOGIC and
# ISERDES mode.
if "IOBDELAY" in params:
value = verilog.unquote(params["IOBDELAY"])
if value == "NONE":
segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0)
segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1)
segmk.add_site_tag(loc, "IDELMUXE3.P0", 0)
segmk.add_site_tag(loc, "IDELMUXE3.P1", 1)
if value == "IBUF":
segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0)
segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1)
segmk.add_site_tag(loc, "IDELMUXE3.P0", 1)
segmk.add_site_tag(loc, "IDELMUXE3.P1", 0)
if value == "IFD":
segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1)
segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0)
segmk.add_site_tag(loc, "IDELMUXE3.P0", 0)
segmk.add_site_tag(loc, "IDELMUXE3.P1", 1)
if value == "BOTH":
segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1)
segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0)
segmk.add_site_tag(loc, "IDELMUXE3.P0", 1)
segmk.add_site_tag(loc, "IDELMUXE3.P1", 0)
if "OFB_USED" in params:
value = verilog.unquote(params["OFB_USED"])
segmk.add_site_tag(
loc, "ISERDES.OFB_USED", int(value == "TRUE"))
# Site used as IDDR
elif verilog.unquote(params["BEL_TYPE"]) in ["IDDR",
"IDDR_NO_CLK"]:
segmk.add_site_tag(loc, "IDDR_OR_ISERDES.IN_USE", 1)
segmk.add_site_tag(loc, "IDDR.IN_USE", 1)
segmk.add_site_tag(loc, "ISERDES.IN_USE", 0)
if "DDR_CLK_EDGE" in params:
value = verilog.unquote(params["DDR_CLK_EDGE"])
segmk.add_site_tag(
loc, "IFF.DDR_CLK_EDGE.OPPOSITE_EDGE",
int(value == "OPPOSITE_EDGE"))
segmk.add_site_tag(
loc, "IFF.DDR_CLK_EDGE.SAME_EDGE",
int(value == "SAME_EDGE"))
segmk.add_site_tag(
loc, "IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED",
int(value == "SAME_EDGE_PIPELINED"))
if "SRTYPE" in params:
value = verilog.unquote(params["SRTYPE"])
if value == "ASYNC":
segmk.add_site_tag(loc, "IFF.SRTYPE.ASYNC", 1)
segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 0)
if value == "SYNC":
segmk.add_site_tag(loc, "IFF.SRTYPE.ASYNC", 0)
segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 1)
if "IDELMUX" in params:
if params["IDELMUX"] == 1:
segmk.add_site_tag(loc, "IDELMUXE3.P0", 1)
segmk.add_site_tag(loc, "IDELMUXE3.P1", 0)
else:
segmk.add_site_tag(loc, "IDELMUXE3.P0", 0)
segmk.add_site_tag(loc, "IDELMUXE3.P1", 1)
if "IFFDELMUX" in params:
if params["IFFDELMUX"] == 1:
segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1)
segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0)
else:
segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0)
segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1)
for inv in ["C", "D"]:
if "IS_{}_INVERTED".format(inv) in params:
segmk.add_site_tag(
loc, "INV_{}".format(inv),
params["IS_{}_INVERTED".format(inv)])
segmk.add_site_tag(
loc, "ZINV_{}".format(inv),
not params["IS_{}_INVERTED".format(inv)])
segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 1)
segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 0)
# Should not happen
else:
print("Unknown BEL_TYPE '{}'".format(params["BEL_TYPE"]))
exit(-1)
# Write segments and tags for later check
def_tags = {t: 0 for d in segmk.site_tags.values() for t in d.keys()}
with open("tags.json", "w") as fp:
tags = {}
for l, d in segmk.site_tags.items():
d1 = dict(def_tags)
d1.update({k: int(v) for k, v in d.items()})
tags[loc_to_tile_site_map[l]] = d1
json.dump(tags, fp, sort_keys=True, indent=1)
def bitfilter(frame_idx, bit_idx):
if frame_idx < 26 or frame_idx > 29:
return False
return True
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
print("Loading tags")
segmk = Segmaker("design.bits")
with open('params.jl', 'r') as f:
design = json.load(f)
for d in design:
site = d['ologic_loc']
handle_data_width(segmk, d)
segmk.add_site_tag(site, 'OSERDES.IN_USE', d['use_oserdese2'])
if d['use_oserdese2']:
segmk.add_site_tag(site, 'OQUSED', 1)
for opt in ['SDR', 'DDR']:
segmk.add_site_tag(
site, 'OSERDES.DATA_RATE_OQ.{}'.format(opt),
verilog.unquote(d['DATA_RATE_OQ']) == opt)
for opt in ['BUF', 'SDR', 'DDR']:
segmk.add_site_tag(
site, 'OSERDES.DATA_RATE_TQ.{}'.format(opt),
verilog.unquote(d['DATA_RATE_TQ']) == opt)
for opt in ['SRVAL_OQ', 'SRVAL_TQ', 'INIT_OQ', 'INIT_TQ']:
segmk.add_site_tag(site, opt, d[opt])
segmk.add_site_tag(site, 'Z' + opt, 1 ^ d[opt])
for opt in ['CLK', 'CLKDIV']:
if d['{}_USED'.format(opt)]:
k = 'IS_{}_INVERTED'.format(opt)
segmk.add_site_tag(site, k, d[k])
segmk.add_site_tag(site, 'ZINV_{}'.format(opt),
1 ^ d[k])
if d['io']:
for idx in range(4):
k = 'IS_T{}_INVERTED'.format(idx + 1)
segmk.add_site_tag(site, k, d[k])
segmk.add_site_tag(site, 'ZINV_T{}'.format(idx + 1),
1 ^ d[k])
for idx in range(8):
k = 'IS_D{}_INVERTED'.format(idx + 1)
segmk.add_site_tag(site, k, d[k])
segmk.add_site_tag(site, 'ZINV_D{}'.format(idx + 1),
1 ^ d[k])
for tristate_width in [1, 4]:
segmk.add_site_tag(
site,
'OSERDES.TRISTATE_WIDTH.W{}'.format(tristate_width),
d['TRISTATE_WIDTH'] == tristate_width)
for opt in ['MASTER', 'SLAVE']:
segmk.add_site_tag(
site, 'OSERDES.SERDES_MODE.{}'.format(opt),
opt == verilog.unquote(d['OSERDES_MODE']))
if d['oddr_mux_config'] == 'direct' and d[
'tddr_mux_config'] == 'direct':
for opt in ['OPPOSITE_EDGE', 'SAME_EDGE']:
segmk.add_site_tag(
site, 'ODDR.DDR_CLK_EDGE.{}'.format(opt),
verilog.unquote(d['ODDR_CLK_EDGE']) == opt)
segmk.add_site_tag(site, 'TDDR.DDR_CLK_EDGE.INV',
d['ODDR_CLK_EDGE'] != d['TDDR_CLK_EDGE'])
segmk.add_site_tag(site, 'TDDR.DDR_CLK_EDGE.ZINV',
d['ODDR_CLK_EDGE'] == d['TDDR_CLK_EDGE'])
if 'SRTYPE' in d:
for opt in ['ASYNC', 'SYNC']:
segmk.add_site_tag(site,
'OSERDES.SRTYPE.{}'.format(opt),
verilog.unquote(d['SRTYPE']) == opt)
for opt in ['ASYNC', 'SYNC']:
segmk.add_site_tag(site, 'OSERDES.TSRTYPE.{}'.format(opt),
verilog.unquote(d['TSRTYPE']) == opt)
if not d['use_oserdese2']:
if d['oddr_mux_config'] == 'lut':
segmk.add_site_tag(site, 'OMUX.D1', 1)
segmk.add_site_tag(site, 'OQUSED', 1)
elif d['oddr_mux_config'] == 'direct':
segmk.add_site_tag(site, 'OMUX.D1', 0)
elif d['oddr_mux_config'] == 'none' and not d['io']:
segmk.add_site_tag(site, 'OQUSED', 0)
segmk.add_site_tag(site, 'TQUSED', d['io'])
if DEBUG_FUZZER:
for k in d:
segmk.add_site_tag(
site, 'param_' + k + '_' +
str(d[k]).replace(' ', '').replace('\n', ''), 1)
segmk.compile(bitfilter=bitfilter)
segmk.write(allow_empty=True)
def main():
print("Loading tags")
segmk = Segmaker("design.bits")
with open('params.jl', 'r') as f:
design = json.load(f)
for d in design:
site = d['site']
handle_data_width(segmk, d)
handle_data_rate(segmk, d)
if 'INTERFACE_TYPE' in d:
for opt in (
'MEMORY',
'MEMORY_DDR3',
'MEMORY_QDR',
'NETWORKING',
'OVERSAMPLE',
):
segmk.add_site_tag(
site, 'ISERDES.INTERFACE_TYPE.{}'.format(opt),
opt == verilog.unquote(d['INTERFACE_TYPE']))
if d['iddr_mux_config'] != 'none':
segmk.add_site_tag(site, 'IFF.ZINIT_Q1', not d['INIT_Q1'])
segmk.add_site_tag(site, 'IFF.ZINIT_Q2', not d['INIT_Q2'])
if 'INIT_Q3' in d:
segmk.add_site_tag(site, 'IFF.ZINIT_Q3', not d['INIT_Q3'])
segmk.add_site_tag(site, 'IFF.ZINIT_Q4', not d['INIT_Q4'])
segmk.add_site_tag(site, 'IFF.ZSRVAL_Q1',
not d['SRVAL_Q1'])
segmk.add_site_tag(site, 'IFF.ZSRVAL_Q2',
not d['SRVAL_Q2'])
segmk.add_site_tag(site, 'IFF.ZSRVAL_Q3',
not d['SRVAL_Q3'])
segmk.add_site_tag(site, 'IFF.ZSRVAL_Q4',
not d['SRVAL_Q4'])
if 'IS_CLK_INVERTED' in d:
if verilog.unquote(d['INTERFACE_TYPE']) == 'MEMORY_DDR3':
segmk.add_site_tag(site, 'IFF.ZINV_CLK',
not d['IS_CLK_INVERTED'])
segmk.add_site_tag(site, 'IFF.ZINV_CLKB',
not d['IS_CLKB_INVERTED'])
segmk.add_site_tag(
site, 'IFF.ZINV_CLK_XOR',
d['IS_CLK_INVERTED'] ^ d['IS_CLKB_INVERTED'])
segmk.add_site_tag(
site, 'IFF.ZINV_CLK_NXOR',
not (d['IS_CLK_INVERTED'] ^ d['IS_CLKB_INVERTED']))
segmk.add_site_tag(
site, 'IFF.ZINV_CLK_OR', d['IS_CLK_INVERTED']
or d['IS_CLKB_INVERTED'])
segmk.add_site_tag(
site, 'IFF.ZINV_CLK_NOR',
not (d['IS_CLK_INVERTED']
or d['IS_CLKB_INVERTED']))
segmk.add_site_tag(
site, 'IFF.ZINV_CLK_AND', d['IS_CLK_INVERTED']
and d['IS_CLKB_INVERTED'])
segmk.add_site_tag(
site, 'IFF.ZINV_CLK_NAND',
not (d['IS_CLK_INVERTED']
and d['IS_CLKB_INVERTED']))
if 'IS_OCLK_INVERTED' in d:
segmk.add_site_tag(site, 'IFF.ZINV_OCLK',
not d['IS_OCLK_INVERTED'])
if 'IS_C_INVERTED' in d:
segmk.add_site_tag(site, 'IFF.ZINV_C',
not d['IS_C_INVERTED'])
segmk.add_site_tag(site, 'ZINV_D', not d['IS_D_INVERTED'])
if 'SRTYPE' in d:
for opt in ['ASYNC', 'SYNC']:
segmk.add_site_tag(site, 'IFF.SRTYPE.{}'.format(opt),
verilog.unquote(d['SRTYPE']) == opt)
if 'DDR_CLK_EDGE' in d:
for opt in [
'OPPOSITE_EDGE', 'SAME_EDGE', 'SAME_EDGE_PIPELINED'
]:
segmk.add_site_tag(
site, 'IFF.DDR_CLK_EDGE.{}'.format(opt),
verilog.unquote(d['DDR_CLK_EDGE']) == opt)
ofb_used = False
if 'OFB_USED' in d and d['OFB_USED']:
ofb_used = True
if d['iddr_mux_config'] == 'direct':
segmk.add_site_tag(site, 'IFFDELMUXE3.0', 0)
segmk.add_site_tag(site, 'IFFDELMUXE3.1', 1)
segmk.add_site_tag(site, 'IFFDELMUXE3.2', 0)
if ofb_used:
segmk.add_site_tag(site, 'IFFMUX.1', 1)
segmk.add_site_tag(site, 'IFFMUX.0', 0)
else:
segmk.add_site_tag(site, 'IFFMUX.1', 0)
segmk.add_site_tag(site, 'IFFMUX.0', 1)
elif d['iddr_mux_config'] == 'idelay':
segmk.add_site_tag(site, 'IFFDELMUXE3.0', 1)
segmk.add_site_tag(site, 'IFFDELMUXE3.1', 0)
segmk.add_site_tag(site, 'IFFDELMUXE3.2', 0)
if ofb_used:
segmk.add_site_tag(site, 'IFFMUX.1', 1)
segmk.add_site_tag(site, 'IFFMUX.0', 0)
else:
segmk.add_site_tag(site, 'IFFMUX.1', 0)
segmk.add_site_tag(site, 'IFFMUX.0', 1)
elif d['iddr_mux_config'] == 'none':
segmk.add_site_tag(site, 'IFFDELMUXE3.0', 0)
segmk.add_site_tag(site, 'IFFDELMUXE3.1', 0)
segmk.add_site_tag(site, 'IFFDELMUXE3.2', 0)
else:
assert False, d['mux_config']
if d['mux_config'] == 'direct':
segmk.add_site_tag(site, 'IDELMUXE3.0', 0)
segmk.add_site_tag(site, 'IDELMUXE3.1', 1)
segmk.add_site_tag(site, 'IDELMUXE3.2', 0)
if ofb_used:
segmk.add_site_tag(site, 'IMUX.1', 1)
segmk.add_site_tag(site, 'IMUX.0', 0)
else:
segmk.add_site_tag(site, 'IMUX.1', 0)
segmk.add_site_tag(site, 'IMUX.0', 1)
elif d['mux_config'] == 'idelay':
segmk.add_site_tag(site, 'IDELMUXE3.0', 1)
segmk.add_site_tag(site, 'IDELMUXE3.1', 0)
segmk.add_site_tag(site, 'IDELMUXE3.2', 0)
if ofb_used:
segmk.add_site_tag(site, 'IMUX.1', 1)
segmk.add_site_tag(site, 'IMUX.0', 0)
else:
segmk.add_site_tag(site, 'IMUX.1', 0)
segmk.add_site_tag(site, 'IMUX.0', 1)
elif d['mux_config'] == 'none':
segmk.add_site_tag(site, 'IDELMUXE3.0', 0)
segmk.add_site_tag(site, 'IDELMUXE3.1', 0)
segmk.add_site_tag(site, 'IDELMUXE3.2', 0)
else:
assert False, d['mux_config']
segmk.compile()
segmk.write(allow_empty=True)
# Can we find instance where they are not aliased?
WA7USED = 0
import sys, re, os
from prjxray.segmaker import Segmaker
segmk = Segmaker("design.bits")
print("Loading tags")
'''
module,loc,c31,b31,a31
my_NDI1MUX_NI_NMC31,SLICE_X12Y100,1,1,0
my_NDI1MUX_NI_NMC31,SLICE_X12Y101,1,1,1
my_NDI1MUX_NI_NMC31,SLICE_X12Y102,1,1,1
'''
f = open('params.csv', 'r')
f.readline()
for l in f:
l = l.strip()
module, loc, c31, b31, a31 = l.split(',')
c31 = int(c31)
b31 = int(b31)
a31 = int(a31)
segmk.add_site_tag(loc, "ADI1MUX.AI", 1 ^ a31)
segmk.add_site_tag(loc, "BDI1MUX.BI", 1 ^ b31)
segmk.add_site_tag(loc, "CDI1MUX.CI", 1 ^ c31)
segmk.compile()
segmk.write()
#
# SPDX-License-Identifier: ISC
from prjxray.segmaker import Segmaker
segmk = Segmaker("design.bits")
print("Loading tags")
'''
name,loc,ce,r
clb_FDRE,SLICE_X12Y100,1,0
clb_FDRE,SLICE_X13Y100,1,1
clb_FDRE,SLICE_X14Y100,1,1
'''
f = open('params.csv', 'r')
f.readline()
for l in f:
name, site, ce, r = l.split(',')
ce = int(ce)
r = int(r)
# Theory: default position are the force positions
# parameter FORCE_CE1=0;
# parameter nFORCE_R0=1;
# .CE(din[0] | FORCE_CE1),
# .R(din[1] & nFORCE_R0),
segmk.add_site_tag(site, "CEUSEDMUX", ce ^ 1)
segmk.add_site_tag(site, "SRUSEDMUX", r)
segmk.compile()
segmk.write()
# FIXME: getting two bits
# 00_40 31_46
# Can we find instance where they are not aliased?
WA7USED = 0
from prjxray.segmaker import Segmaker
segmk = Segmaker("design.bits")
print("Loading tags")
'''
module,loc,c31,b31,a31
my_NDI1MUX_NI_NMC31,SLICE_X12Y100,1,1,0
my_NDI1MUX_NI_NMC31,SLICE_X12Y101,1,1,1
my_NDI1MUX_NI_NMC31,SLICE_X12Y102,1,1,1
'''
f = open('params.csv', 'r')
f.readline()
for l in f:
l = l.strip()
module, loc, c31, b31, a31 = l.split(',')
c31 = int(c31)
b31 = int(b31)
a31 = int(a31)
segmk.add_site_tag(loc, "ALUT.DI1MUX.AI", 1 ^ a31)
segmk.add_site_tag(loc, "BLUT.DI1MUX.BI", 1 ^ b31)
segmk.add_site_tag(loc, "CLUT.DI1MUX.CI", 1 ^ c31)
segmk.compile()
segmk.write()
def main():
print("Loading tags")
segmk = Segmaker("design.bits")
with open('params.jl', 'r') as f:
design = json.load(f)
for d in design:
site = d['ilogic_loc']
handle_data_width(segmk, d)
handle_data_rate(segmk, d)
segmk.add_site_tag(site, 'ISERDES.IN_USE', d['use_iserdese2'])
if 'NUM_CE' in d:
segmk.add_site_tag(site, 'ISERDES.NUM_CE.N2', d['NUM_CE'] == 2)
segmk.add_site_tag(
site, 'IDDR_OR_ISERDES.IN_USE', d['use_iserdese2']
or d['iddr_mux_config'] != 'none')
if 'INTERFACE_TYPE' in d:
for opt in (
'MEMORY',
'MEMORY_DDR3',
'MEMORY_QDR',
'NETWORKING',
'OVERSAMPLE',
):
segmk.add_site_tag(
site, 'ISERDES.INTERFACE_TYPE.{}'.format(opt),
opt == verilog.unquote(d['INTERFACE_TYPE']))
segmk.add_site_tag(
site, 'ISERDES.INTERFACE_TYPE.Z_{}'.format(opt),
opt != verilog.unquote(d['INTERFACE_TYPE']))
segmk.add_site_tag(
site, 'ISERDES.INTERFACE_TYPE.NOT_MEMORY', 'MEMORY'
not in verilog.unquote(d['INTERFACE_TYPE']))
if d['iddr_mux_config'] != 'none':
segmk.add_site_tag(site, 'IFF.ZINIT_Q1', not d['INIT_Q1'])
segmk.add_site_tag(site, 'IFF.ZINIT_Q2', not d['INIT_Q2'])
if 'DYN_CLKDIV_INV_EN' in d:
segmk.add_site_tag(
site, 'DYN_CLKDIV_INV_EN',
verilog.unquote(d['DYN_CLKDIV_INV_EN']) == 'TRUE')
if 'DYN_CLK_INV_EN' in d:
segmk.add_site_tag(
site, 'DYN_CLK_INV_EN',
verilog.unquote(d['DYN_CLK_INV_EN']) == 'TRUE')
if 'INIT_Q3' in d:
segmk.add_site_tag(site, 'IFF.ZINIT_Q3', not d['INIT_Q3'])
segmk.add_site_tag(site, 'IFF.ZINIT_Q4', not d['INIT_Q4'])
segmk.add_site_tag(site, 'IFF.ZSRVAL_Q1',
not d['SRVAL_Q1'])
segmk.add_site_tag(site, 'IFF.ZSRVAL_Q2',
not d['SRVAL_Q2'])
segmk.add_site_tag(site, 'IFF.ZSRVAL_Q3',
not d['SRVAL_Q3'])
segmk.add_site_tag(site, 'IFF.ZSRVAL_Q4',
not d['SRVAL_Q4'])
if 'IS_CLK_INVERTED' in d and not d['DISABLE_CLOCKS']:
if verilog.unquote(d['INTERFACE_TYPE']) == 'MEMORY_DDR3':
segmk.add_site_tag(site, 'IFF.INV_CLK',
d['IS_CLK_INVERTED'])
segmk.add_site_tag(site, 'IFF.INV_CLKB',
d['IS_CLKB_INVERTED'])
segmk.add_site_tag(site, 'IFF.ZINV_CLK',
not d['IS_CLK_INVERTED'])
segmk.add_site_tag(site, 'IFF.ZINV_CLKB',
not d['IS_CLKB_INVERTED'])
segmk.add_site_tag(
site, 'IFF.ZINV_CLK_XOR',
d['IS_CLK_INVERTED'] ^ d['IS_CLKB_INVERTED'])
segmk.add_site_tag(
site, 'IFF.ZINV_CLK_NXOR',
not (d['IS_CLK_INVERTED'] ^ d['IS_CLKB_INVERTED']))
segmk.add_site_tag(
site, 'IFF.ZINV_CLK_OR', d['IS_CLK_INVERTED']
or d['IS_CLKB_INVERTED'])
segmk.add_site_tag(
site, 'IFF.ZINV_CLK_NOR',
not (d['IS_CLK_INVERTED']
or d['IS_CLKB_INVERTED']))
segmk.add_site_tag(
site, 'IFF.ZINV_CLK_AND', d['IS_CLK_INVERTED']
and d['IS_CLKB_INVERTED'])
segmk.add_site_tag(
site, 'IFF.ZINV_CLK_NAND',
not (d['IS_CLK_INVERTED']
and d['IS_CLKB_INVERTED']))
if 'IS_OCLK_INVERTED' in d and not d['DISABLE_CLOCKS']:
segmk.add_site_tag(site, 'IFF.INV_OCLK',
d['IS_OCLK_INVERTED'])
segmk.add_site_tag(site, 'IFF.ZINV_OCLK',
not d['IS_OCLK_INVERTED'])
segmk.add_site_tag(site, 'IFF.INV_OCLKB',
d['IS_OCLKB_INVERTED'])
segmk.add_site_tag(site, 'IFF.ZINV_OCLKB',
not d['IS_OCLKB_INVERTED'])
if 'IS_CLKDIV_INVERTED' in d and not d['DISABLE_CLOCKS'] and \
verilog.unquote(d['INTERFACE_TYPE']) == 'MEMORY':
segmk.add_site_tag(site, 'IFF.INV_CLKDIV',
d['IS_CLKDIV_INVERTED'])
segmk.add_site_tag(site, 'IFF.ZINV_CLKDIV',
not d['IS_CLKDIV_INVERTED'])
if 'IS_C_INVERTED' in d:
segmk.add_site_tag(site, 'IFF.ZINV_C',
not d['IS_C_INVERTED'])
segmk.add_site_tag(site, 'ZINV_D', not d['IS_D_INVERTED'])
if 'SRTYPE' in d:
for opt in ['ASYNC', 'SYNC']:
segmk.add_site_tag(site, 'IFF.SRTYPE.{}'.format(opt),
verilog.unquote(d['SRTYPE']) == opt)
if 'DDR_CLK_EDGE' in d:
for opt in [
'OPPOSITE_EDGE', 'SAME_EDGE', 'SAME_EDGE_PIPELINED'
]:
segmk.add_site_tag(
site, 'IFF.DDR_CLK_EDGE.{}'.format(opt),
verilog.unquote(d['DDR_CLK_EDGE']) == opt)
if d['iddr_mux_config'] == 'direct':
segmk.add_site_tag(site, 'IFFDELMUXE3.P0', 0)
segmk.add_site_tag(site, 'IFFDELMUXE3.P1', 1)
segmk.add_site_tag(site, 'IFFDELMUXE3.P2', 0)
elif d['iddr_mux_config'] == 'idelay':
segmk.add_site_tag(site, 'IFFDELMUXE3.P0', 1)
segmk.add_site_tag(site, 'IFFDELMUXE3.P1', 0)
segmk.add_site_tag(site, 'IFFDELMUXE3.P2', 0)
elif d['iddr_mux_config'] == 'none':
segmk.add_site_tag(site, 'IFFDELMUXE3.P0', 0)
segmk.add_site_tag(site, 'IFFDELMUXE3.P1', 0)
segmk.add_site_tag(site, 'IFFDELMUXE3.P2', 0)
else:
assert False, d['mux_config']
if d['mux_config'] == 'direct':
segmk.add_site_tag(site, 'IDELMUXE3.P0', 0)
segmk.add_site_tag(site, 'IDELMUXE3.P1', 1)
segmk.add_site_tag(site, 'IDELMUXE3.P2', 0)
elif d['mux_config'] == 'idelay':
segmk.add_site_tag(site, 'IDELMUXE3.P0', 1)
segmk.add_site_tag(site, 'IDELMUXE3.P1', 0)
segmk.add_site_tag(site, 'IDELMUXE3.P2', 0)
elif d['mux_config'] == 'none':
segmk.add_site_tag(site, 'IDELMUXE3.P0', 0)
segmk.add_site_tag(site, 'IDELMUXE3.P1', 0)
segmk.add_site_tag(site, 'IDELMUXE3.P2', 0)
else:
assert False, d['mux_config']
if DEBUG_FUZZER:
for k in d:
segmk.add_site_tag(
site, 'param_' + k + '_' +
str(d[k]).replace(' ', '').replace('\n', ''), 1)
segmk.compile(bitfilter=bitfilter)
segmk.write(allow_empty=True)
import sys, re
from prjxray.segmaker import Segmaker
segmk = Segmaker("design.bits")
print("Loading tags")
'''
module,loc,n,def_a
clb_N5FFMUX,SLICE_X12Y100,3,1
clb_N5FFMUX,SLICE_X13Y100,0,1
clb_N5FFMUX,SLICE_X14Y100,3,1
'''
f = open('params.csv', 'r')
f.readline()
for l in f:
module, loc, n, def_a = l.split(',')
def_a = int(def_a)
n = int(n)
#which = chr(ord('A') + n)
for i, which in enumerate('ABCD'):
# Theory: there is one bit for each mux positon
# In each config 3 muxes are in one position, other 3 are in another
inv = int(i == n)
segmk.add_site_tag(loc, "%c5FFMUX.IN_A" % which, def_a ^ inv)
segmk.add_site_tag(loc, "%c5FFMUX.IN_B" % which, 1 ^ def_a ^ inv)
segmk.compile()
segmk.write()
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
from prjxray.segmaker import Segmaker
segmk = Segmaker("design.bits")
print("Loading tags")
'''
module,loc,bel,n
clb_NCY0_MX,SLICE_X12Y100,A6LUT,3
clb_NCY0_O5,SLICE_X16Y100,C6LUT,0
clb_NCY0_O5,SLICE_X17Y100,A6LUT,2
'''
f = open('params.csv', 'r')
f.readline()
for l in f:
module, loc, bel, n = l.split(',')
n = int(n)
# A, B, etc
which = bel[0]
# One bit, set on O5
segmk.add_site_tag(loc, "CARRY4.%cCY0" % which, module == 'clb_NCY0_O5')
segmk.compile()
segmk.write()
print("Loading tags")
'''
module,loc,bela,belb,belc,beld
my_ram_N,SLICE_X12Y100,SRLC32E,SRL16E,SRLC32E,LUT6
my_ram_N,SLICE_X12Y101,SRLC32E,SRLC32E,SRLC32E,SRLC32E
my_RAM256X1S,SLICE_X12Y102,None,0,,
'''
f = open('params.csv', 'r')
f.readline()
for l in f:
l = l.strip()
module, loc, p0, p1, p2, p3 = l.split(',')
segmk.add_site_tag(
loc, "WA7USED", module
in ('my_RAM128X1D', 'my_RAM128X1S_N', 'my_RAM256X1S'))
segmk.add_site_tag(loc, "WA8USED", module == 'my_RAM256X1S')
bels_tcl = [design.get("%s/%c6LUT" % (loc, bel), None) for bel in "ABCD"]
# (a, b, c, d)
# Size set for RAM32X1S, RAM32X1D, and SRL16E
size = [0, 0, 0, 0]
# SRL set for SRL* primitives
srl = [0, 0, 0, 0]
# RAM set for RAM* primitives
ram = [0, 0, 0, 0]
verbose and print('%s' % loc)
verbose and print(' %s %s %s %s' % tuple(bels_tcl))
#!/usr/bin/env python3
import sys
from prjxray.segmaker import Segmaker
segmk = Segmaker("design_%s.bits" % sys.argv[1])
print("Loading tags from design_%s.txt." % sys.argv[1])
with open("design_%s.txt" % sys.argv[1], "r") as f:
for line in f:
line = line.split()
site = line[0]
bel = line[1]
init = int(line[2][4:], 16)
for i in range(64):
bitname = "%s.INIT[%02d]" % (bel, i)
bitname = bitname.replace("6LUT", "LUT")
segmk.add_site_tag(site, bitname, ((init >> i) & 1) != 0)
segmk.compile()
segmk.write(sys.argv[1])
def main():
segmk = Segmaker("design.bits")
fuz_dir = os.getenv("FUZDIR", None)
assert fuz_dir
with open(os.path.join(fuz_dir, "attrs.json"), "r") as attr_file:
attrs = json.load(attr_file)
print("Loading tags")
with open("params.json") as f:
primitives_list = json.load(f)
for primitive in primitives_list:
tile_type = primitive["tile_type"]
params_list = primitive["params"]
for params in params_list:
site = params["site"]
if "GTPE2_CHANNEL" not in site:
continue
in_use = params["IN_USE"]
segmk.add_site_tag(site, "IN_USE", in_use)
if in_use:
for param, param_info in attrs.items():
value = params[param]
param_type = param_info["type"]
param_digits = param_info["digits"]
param_values = param_info["values"]
if param_type == INT:
param_encodings = param_info["encoding"]
param_encoding = param_encodings[param_values.index(
value)]
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=param_encoding, digits=param_digits)
[::-1]
]
for i in range(param_digits):
segmk.add_site_tag(site, '%s[%u]' % (param, i),
bitstr[i])
elif param_type == BIN:
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=value, digits=param_digits)[::-1]
]
for i in range(param_digits):
segmk.add_site_tag(site, "%s[%u]" % (param, i),
bitstr[i])
elif param_type == BOOL:
segmk.add_site_tag(site, param, value == "TRUE")
else:
assert param_type == STR
# The RXSLIDE_MODE parameter has overlapping bits
# for its possible values. We need to treat it
# differently
if param == "RXSLIDE_MODE":
add_site_group_zero(segmk, site,
"{}.".format(param),
param_values, "OFF", value)
else:
for param_value in param_values:
segmk.add_site_tag(
site, "{}.{}".format(param, param_value),
value == param_value)
for param in [
"TXUSRCLK", "TXUSRCLK2", "TXPHDLYTSTCLK",
"SIGVALIDCLK", "RXUSRCLK", "RXUSRCLK2", "DRPCLK",
"DMONITORCLK", "CLKRSVD0", "CLKRSVD1"
]:
segmk.add_site_tag(site, "INV_" + param, params[param])
gtp_channel_x = [
"GTP_CHANNEL_0",
"GTP_CHANNEL_1",
"GTP_CHANNEL_2",
"GTP_CHANNEL_3",
]
gtp_channel_x_mid = [
"GTP_CHANNEL_0_MID_LEFT",
"GTP_CHANNEL_1_MID_LEFT",
"GTP_CHANNEL_2_MID_LEFT",
"GTP_CHANNEL_3_MID_LEFT",
"GTP_CHANNEL_0_MID_RIGHT",
"GTP_CHANNEL_1_MID_RIGHT",
"GTP_CHANNEL_2_MID_RIGHT",
"GTP_CHANNEL_3_MID_RIGHT",
]
if tile_type in gtp_channel_x:
bitfilter = bitfilter_gtp_channel_x
elif tile_type in gtp_channel_x_mid:
bitfilter = bitfilter_gtp_channel_x_mid
else:
assert False, tile_type
segmk.compile(bitfilter=bitfilter)
segmk.write()
# rewrite name of F78 source net: MUXes A and C have an F7 input, MUX B has an F8 input
if src == "F78":
if which in "AC":
src = "F7"
elif which == "B":
src = "F8"
else:
assert 0
# rewrite name of B5Q source net: It's actually A5Q, B5Q, C5Q, or D5Q
if src == "B5Q":
src = which + "5Q"
# add the 1-tag for this connection
tag = "%sOUTMUX.%s" % (which, src)
segmk.add_site_tag(loc, tag, 1)
# remove this MUX from the cache, preventing generation of 0-tags for this MUX
cache[loc].remove(which)
# O6 hack per https://github.com/SymbiFlow/prjxray/issues/243
segmk.add_site_tag(loc, "%sOUTMUX.%s" % (which, "O6"), src == "O5")
# create 0-tags for all sources on the remaining (unused) MUXes
for loc, muxes in cache.items():
for which in muxes:
for src in "F7 F8 CY O5 XOR 5Q".split():
if src == "F7" and which not in "AC": continue
if src == "F8" and which not in "B": continue
if src == "5Q": src = which + "5Q"
tag = "%sOUTMUX.%s" % (which, src)
cel_name = line[7]
# ex: FDCE
cel_prim = line[8]
# 1'b1
# cinv = int(line[9][-1])
cinv = int(line[9])
init = vs2i(line[10])
#init = int(line[10])
# A B C D
which = ff_name[0]
# LUT6 vs LUT5 FF
is5 = '5' in ff_name
if used:
segmk.add_site_tag(site, "%s.ZINI" % ff_name, 1 ^ init)
# CLKINV turns out to be more complicated than origianlly thought
if isff(cel_prim):
segmk.add_site_tag(site, "CLKINV", cinv)
else:
segmk.add_site_tag(site, "CLKINV", 1 ^ cinv)
# Synchronous vs asynchronous FF
# Unlike most bits, shared between all CLB FFs
segmk.add_site_tag(site, "FFSYNC", cel_prim in ('FDSE', 'FDRE'))
# Latch bit
# Only applies to LUT6 (non-5) FF's
if not is5:
segmk.add_site_tag(site, "LATCH", isl(cel_prim))
def main():
segmk = Segmaker("design.bits", verbose=True)
# Load tags
with open("params.json", "r") as fp:
data = json.load(fp)
idelay_types = ["FIXED", "VARIABLE", "VAR_LOAD"]
delay_srcs = ["IDATAIN", "DATAIN"]
# Output tags
for params in data:
segmk.add_site_tag(params['IDELAY_IN_USE'], 'IN_USE', True)
segmk.add_site_tag(params['IDELAY_NOT_IN_USE'], 'IN_USE', False)
loc = verilog.unquote(params["LOC"])
# Delay type
value = verilog.unquote(params["IDELAY_TYPE"])
value = value.replace("_PIPE",
"") # VAR_LOAD and VAR_LOAD_PIPE are the same
add_site_group_zero(segmk, loc, "IDELAY_TYPE_", idelay_types, "FIXED",
value)
# Delay value
value = int(params["IDELAY_VALUE"])
for i in range(5):
segmk.add_site_tag(loc, "IDELAY_VALUE[%01d]" % i,
((value >> i) & 1) != 0)
segmk.add_site_tag(loc, "ZIDELAY_VALUE[%01d]" % i,
((value >> i) & 1) == 0)
# Delay source
value = verilog.unquote(params["DELAY_SRC"])
for x in delay_srcs:
segmk.add_site_tag(loc, "DELAY_SRC_%s" % x, int(value == x))
value = verilog.unquote(params["CINVCTRL_SEL"])
segmk.add_site_tag(loc, "CINVCTRL_SEL", int(value == "TRUE"))
value = verilog.unquote(params["PIPE_SEL"])
segmk.add_site_tag(loc, "PIPE_SEL", int(value == "TRUE"))
if "IS_C_INVERTED" in params:
segmk.add_site_tag(loc, "IS_C_INVERTED",
int(params["IS_C_INVERTED"]))
segmk.add_site_tag(loc, "ZINV_C", 1 ^ int(params["IS_C_INVERTED"]))
segmk.add_site_tag(loc, "IS_DATAIN_INVERTED",
int(params["IS_DATAIN_INVERTED"]))
if params['IBUF_IN_USE']:
value = verilog.unquote(params["HIGH_PERFORMANCE_MODE"])
segmk.add_site_tag(loc, "HIGH_PERFORMANCE_MODE",
int(value == "TRUE"))
segmk.add_site_tag(loc, "IS_IDATAIN_INVERTED",
int(params["IS_IDATAIN_INVERTED"]))
segmk.compile(bitfilter=bitfilter)
segmk.write()
WA7USED = 0
from prjxray.segmaker import Segmaker
segmk = Segmaker("design.bits")
print("Loading tags")
'''
module,loc,c31,b31,a31
my_NDI1MUX_NI_NMC31,SLICE_X12Y100,1,1,0
my_NDI1MUX_NI_NMC31,SLICE_X12Y101,1,1,1
my_NDI1MUX_NI_NMC31,SLICE_X12Y102,1,1,1
'''
f = open('params.csv', 'r')
f.readline()
for l in f:
l = l.strip()
module, loc, c31, b31, a31 = l.split(',')
c31 = int(c31)
b31 = int(b31)
a31 = int(a31)
segmk.add_site_tag(loc, "ALUT.DI1MUX.AI", 1 ^ a31)
segmk.add_site_tag(loc, "ALUT.DI1MUX.BDI1_BMC31", a31)
segmk.add_site_tag(loc, "BLUT.DI1MUX.BI", 1 ^ b31)
segmk.add_site_tag(loc, "BLUT.DI1MUX.DI_CMC31", b31)
segmk.add_site_tag(loc, "CLUT.DI1MUX.CI", 1 ^ c31)
segmk.add_site_tag(loc, "CLUT.DI1MUX.DI_DMC31", c31)
segmk.compile()
segmk.write()
def main():
print("Loading tags")
segmk = Segmaker("design.bits")
'''
port,site,tile,pin,slew,drive,pulltype
di[0],IOB_X0Y107,LIOB33_X0Y107,A21,PULLDOWN
di[10],IOB_X0Y147,LIOB33_X0Y147,F14,PULLUP
'''
with open('params.jl', 'r') as f:
design = json.load(f)
for d in design:
site = d['site']
if skip_broken_tiles(d):
continue
iostandard = verilog.unquote(d['IOSTANDARD'])
stepdown = iostandard in STEPDOWN_IOSTANDARDS
segmk.add_site_tag(site, '_'.join(STEPDOWN_IOSTANDARDS), stepdown)
if d['type'] is None:
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
for drive in drives_for_iostandard(iostandard):
segmk.add_site_tag(
site,
'{}.DRIVE.I{}.IN_OUT_COMMON'.format(iostandard,
drive), 0)
elif d['type'] == 'IBUF':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
for drive in drives_for_iostandard(iostandard):
segmk.add_site_tag(
site,
'{}.DRIVE.I{}.IN_OUT_COMMON'.format(iostandard,
drive), 1)
elif d['type'] == 'OBUF':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
for drive in drives_for_iostandard(iostandard):
if drive == d['DRIVE']:
segmk.add_site_tag(
site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
iostandard, drive), 1)
else:
segmk.add_site_tag(
site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
iostandard, drive), 0)
elif d['type'] == 'IOBUF_INTERMDISABLE':
segmk.add_site_tag(site, 'INOUT', 1)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
if d['type'] is not None:
segmaker.add_site_group_zero(
segmk, site, "PULLTYPE.",
("NONE", "KEEPER", "PULLDOWN", "PULLUP"), "PULLDOWN",
verilog.unquote(d['PULLTYPE']))
if d['type'] == 'IBUF' or d['type'] is None:
continue
drive_opts = set()
for opt in ("LVCMOS25", "LVCMOS33", "LVCMOS18", "LVCMOS15",
"LVCMOS12", 'LVTTL'):
for drive_opt in ("4", "8", "12", "16", "24"):
if drive_opt == "16" and opt == "LVCMOS12":
continue
if drive_opt == "24" and opt not in ["LVCMOS18", 'LVTTL']:
continue
drive_opts.add(mk_drive_opt(opt, drive_opt))
segmaker.add_site_group_zero(segmk, site, '', drive_opts,
mk_drive_opt('LVCMOS25', '12'),
mk_drive_opt(iostandard, d['DRIVE']))
segmaker.add_site_group_zero(segmk, site, "SLEW.",
("SLOW", "FAST"), "FAST",
verilog.unquote(d['SLEW']))
if 'ibufdisable_wire' in d:
segmk.add_site_tag(site, 'IBUFDISABLE.I',
d['ibufdisable_wire'] != '0')
if 'intermdisable_wire' in d:
segmk.add_site_tag(site, 'INTERMDISABLE.I',
d['intermdisable_wire'] != '0')
segmk.compile(bitfilter=bitfilter)
segmk.write(allow_empty=True)
def main():
segmk = Segmaker("design.bits")
fuz_dir = os.getenv("FUZDIR", None)
assert fuz_dir
with open(os.path.join(fuz_dir, "attrs.json"), "r") as attr_file:
attrs = json.load(attr_file)
print("Loading tags")
with open("params.json") as f:
params_dict = json.load(f)
tile_type = params_dict["tile_type"]
params_list = params_dict["params"]
for params in params_list:
site = params["site"]
tile = params["tile"]
if "GTPE2_COMMON" not in site:
continue
in_use = params["IN_USE"]
segmk.add_site_tag(site, "IN_USE", in_use)
if in_use:
for param, param_info in attrs.items():
value = params[param]
param_type = param_info["type"]
param_digits = param_info["digits"]
param_values = param_info["values"]
if param_type == INT:
param_encodings = param_info["encoding"]
param_encoding = param_encodings[param_values.index(value)]
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=param_encoding, digits=param_digits)[::-1]
]
for i in range(param_digits):
segmk.add_site_tag(site, '%s[%u]' % (param, i),
bitstr[i])
else:
assert param_type == BIN
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=value, digits=param_digits)[::-1]
]
for i in range(param_digits):
segmk.add_site_tag(site, "%s[%u]" % (param, i),
bitstr[i])
for param in ["PLL0LOCKDETCLK", "PLL1LOCKDETCLK", "DRPCLK"]:
segmk.add_site_tag(site, "ZINV_" + param, 1 ^ params[param])
for param in [
"GTREFCLK0_USED", "GTREFCLK1_USED", "BOTH_GTREFCLK_USED"
]:
segmk.add_site_tag(site, param, params[param])
segmk.add_tile_tag(tile, "ENABLE_DRP", params["ENABLE_DRP"])
for params in params_list:
site = params["site"]
if "IBUFDS_GTE2" not in site:
continue
in_use = params["IN_USE"]
segmk.add_site_tag(site, "IN_USE", in_use)
if in_use:
tile = params["tile"]
for param in ["CLKRCV_TRST", "CLKCM_CFG"]:
value = params[param]
segmk.add_site_tag(site, param, "TRUE" in value)
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=params["CLKSWING_CFG"], digits=2)[::-1]
]
for i in range(2):
segmk.add_tile_tag(tile, "IBUFDS_GTE2.%s[%u]" % (param, i),
bitstr[i])
if tile_type.startswith("GTP_COMMON_MID"):
bitfilter = bitfilter_gtp_common_mid
elif tile_type == "GTP_COMMON":
bitfilter = bitfilter_gtp_common
else:
assert False, tile_type
segmk.compile(bitfilter=bitfilter)
segmk.write()
