def main():
segmk = Segmaker("design.bits")
tiledata = {}
pipdata = {}
ignpip = set()
tile_ports = {}
read_pip_data('gtp_common_mid_ck_mux.txt', pipdata, tile_ports)
print("Loading tags from design.txt.")
with open("design.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
if not tile.startswith('GTP_COMMON_MID'):
continue
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set()
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
if "HCLK_GTP_CK_MUX" not in src:
ignpip.add((src, dst))
for tile, pips_srcs_dsts in tiledata.items():
tile_type = pips_srcs_dsts["type"]
pips = pips_srcs_dsts["pips"]
for src, dst in pipdata["GTP_COMMON"]:
if (src, dst) in ignpip:
pass
elif (src, dst) in pips:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
elif src not in tiledata[tile]["srcs"] and dst not in tiledata[
tile]["dsts"]:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
segmk.set_def_bt('BLOCK_RAM')
print("Loading tags")
'''
'''
with open('params.json') as f:
params = json.load(f)
for param in params:
for initp in range(NUM_INITP_PARAMS):
p = 'INITP_{:02X}'.format(initp)
val = param[p]
for bit in range(BITS_PER_PARAM):
segmk.add_site_tag(
param['site'], "{p}[{bit:03d}]".format(
p=p,
bit=bit,
), val & (1 << bit) != 0)
for init in range(NUM_INIT_PARAMS):
p = 'INIT_{:02X}'.format(init)
val = param[p]
for bit in range(BITS_PER_PARAM):
segmk.add_site_tag(
param['site'], "{p}[{bit:03d}]".format(
p=p,
bit=bit,
), val & (1 << bit) != 0)
segmk.compile()
segmk.write()
def handle_design(prefix, second_pass):
segmk = Segmaker(prefix + ".bits")
tiledata = dict()
nlines = 0
print("Loading tags from design.txt.")
with open(prefix + ".txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
_, pip = pip.split(".")
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {"pips": set(), "srcs": set(), "dsts": set()}
if pip in pipdata:
assert pipdata[pip] == (src, dst)
else:
pipdata[pip] = (src, dst)
tiledata[tile]["pips"].add(pip)
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
if pnum == 1 or pdir == 0 or \
re.match(r"^(L[HV]B?)(_L)?(_B)?[0-9]", src) or \
re.match(r"^(L[HV]B?)(_L)?(_B)?[0-9]", dst) or \
re.match(r"^(CTRL|GFAN)(_L)?[0-9]", dst):
ignpip.add(pip)
nlines += 1
if nlines == 0:
return
for tile, pips_srcs_dsts in tiledata.items():
pips = pips_srcs_dsts["pips"]
srcs = pips_srcs_dsts["srcs"]
dsts = pips_srcs_dsts["dsts"]
for pip, src_dst in pipdata.items():
src, dst = src_dst
if pip in ignpip:
pass
elif pip in pips:
segmk.addtag(tile, "%s.%s" % (dst, src), 1)
elif src_dst[1] not in dsts:
segmk.addtag(tile, "%s.%s" % (dst, src), 0)
if second_pass:
segmk.compile()
segmk.write(prefix[7:])
def main():
segmk = Segmaker("design.bits")
fuz_dir = os.getenv("FUZDIR", None)
assert fuz_dir
with open(os.path.join(fuz_dir, "attrs.json"), "r") as attr_file:
attrs = json.load(attr_file)
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
site = params['site']
for param, param_info in attrs.items():
value = params[param]
param_type = param_info["type"]
param_digits = param_info["digits"]
param_values = param_info["values"]
if param_type == BIN:
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=value, digits=param_digits)[::-1]
]
for i in range(param_digits):
segmk.add_site_tag(site, "%s[%u]" % (param, i), bitstr[i])
else:
assert param_type == BOOL
segmk.add_site_tag(site, param, value == "TRUE")
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
for row in params:
base_name = 'BUFR_Y{}'.format(row['y'])
segmk.add_tile_tag(
row['tile'], '{}.IN_USE'.format(base_name), row['IN_USE'])
if not row['IN_USE']:
continue
segmk.add_tile_tag(
row['tile'], '{}.BUFR_DIVIDE.BYPASS'.format(base_name),
'"BYPASS"' == row['BUFR_DIVIDE'])
for opt in range(1, 9):
if row['BUFR_DIVIDE'] == str(opt):
segmk.add_tile_tag(
row['tile'], '{}.BUFR_DIVIDE.D{}'.format(base_name, opt),
1)
elif '"BYPASS"' == row['BUFR_DIVIDE']:
segmk.add_tile_tag(
row['tile'], '{}.BUFR_DIVIDE.D{}'.format(base_name, opt),
0)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
site = params['site']
for param, _ in boolean_params:
value = params[param]
segmk.add_site_tag(site, param, value)
for param, digits in hex_params + int_params:
value = int(params[param])
bitstr = [
int(x)
for x in "{value:0{digits}b}".format(value=value,
digits=digits)[::-1]
]
for i in range(digits):
segmk.add_site_tag(site, '%s[%u]' % (param, i), bitstr[i])
segmk.compile(bitfilter=bitfilter)
segmk.write()
def run():
segmk = Segmaker("design.bits")
clk_inverts = {}
with open('design.csv', 'r') as f:
for params in csv.DictReader(f):
clk_inverts[params['site']] = params
print("Loading tags")
f = open('params.jl', 'r')
f.readline()
for l in f:
j = json.loads(l)
ps = j['params']
assert j['module'] == 'my_RAMB18E1'
site = verilog.unquote(ps['LOC'])
isinv_tags(segmk, ps, site, clk_inverts[site])
bus_tags(segmk, ps, site)
rw_width_tags(segmk, ps, site)
write_mode_tags(segmk, ps, site)
write_rstreg_priority(segmk, ps, site)
write_rdaddr_collision(segmk, ps, site)
def bitfilter(frame, bit):
# rw_width_tags() aliasing interconnect on large widths
return frame not in (20, 21)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
for tile_param in params:
if tile_param['BRAM36_IN_USE']:
write_ram_ext_tags(segmk, tile_param)
segmk.add_site_tag(tile_param['site'], 'EN_ECC_READ',
tile_param['EN_ECC_READ'])
segmk.add_site_tag(tile_param['site'], 'EN_ECC_WRITE',
tile_param['EN_ECC_WRITE'])
for ab in 'ab':
for rw in 'rw':
if rw == 'r':
dir = 'READ'
else:
dir = 'WRITE'
width = tile_param['bram36_{}{}_width'.format(rw, ab)]
tag = 'BRAM36_{}_WIDTH_{}_1'.format(dir, ab.upper())
if width == 1:
segmk.add_site_tag(tile_param['site'], tag,
tile_param['BRAM36_IN_USE'])
segmk.compile()
segmk.write()
def main():
segmk = Segmaker("design.bits")
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
for row in params:
base_name = 'BUFHCE_X{}Y{}'.format(row['x'], row['y'])
segmk.add_site_tag(row['site'], '{}.IN_USE'.format(base_name),
row['IN_USE'])
if not row['IN_USE']:
continue
segmk.add_site_tag(row['site'], '{}.INIT_OUT'.format(base_name),
row['INIT_OUT'])
segmk.add_site_tag(row['site'], '{}.ZINV_CE'.format(base_name),
1 ^ row['IS_CE_INVERTED'])
# SYNC is a zero pattern
for opt in ['ASYNC']:
segmk.add_site_tag(row['site'],
'{}.CE_TYPE.'.format(base_name) + opt,
verilog.unquote(row['CE_TYPE']) == opt)
segmk.compile()
segmk.write()
def main():
segmk = Segmaker("design.bits", verbose=True)
# Load tags
with open("params.json", "r") as fp:
data = json.load(fp)
idelay_types = ["FIXED", "VARIABLE", "VAR_LOAD"]
delay_srcs = ["IDATAIN", "DATAIN"]
# Output tags
for params in data:
segmk.add_site_tag(params['IDELAY_IN_USE'], 'IN_USE', True)
segmk.add_site_tag(params['IDELAY_NOT_IN_USE'], 'IN_USE', False)
loc = verilog.unquote(params["LOC"])
# Delay type
value = verilog.unquote(params["IDELAY_TYPE"])
value = value.replace("_PIPE",
"") # VAR_LOAD and VAR_LOAD_PIPE are the same
add_site_group_zero(segmk, loc, "IDELAY_TYPE_", idelay_types, "FIXED",
value)
# Delay value
value = int(params["IDELAY_VALUE"])
for i in range(5):
segmk.add_site_tag(loc, "IDELAY_VALUE[%01d]" % i,
((value >> i) & 1) != 0)
segmk.add_site_tag(loc, "ZIDELAY_VALUE[%01d]" % i,
((value >> i) & 1) == 0)
# Delay source
value = verilog.unquote(params["DELAY_SRC"])
for x in delay_srcs:
segmk.add_site_tag(loc, "DELAY_SRC_%s" % x, int(value == x))
value = verilog.unquote(params["CINVCTRL_SEL"])
segmk.add_site_tag(loc, "CINVCTRL_SEL", int(value == "TRUE"))
value = verilog.unquote(params["PIPE_SEL"])
segmk.add_site_tag(loc, "PIPE_SEL", int(value == "TRUE"))
if "IS_C_INVERTED" in params:
segmk.add_site_tag(loc, "IS_C_INVERTED",
int(params["IS_C_INVERTED"]))
segmk.add_site_tag(loc, "ZINV_C", 1 ^ int(params["IS_C_INVERTED"]))
segmk.add_site_tag(loc, "IS_DATAIN_INVERTED",
int(params["IS_DATAIN_INVERTED"]))
if params['IBUF_IN_USE']:
value = verilog.unquote(params["HIGH_PERFORMANCE_MODE"])
segmk.add_site_tag(loc, "HIGH_PERFORMANCE_MODE",
int(value == "TRUE"))
segmk.add_site_tag(loc, "IS_IDATAIN_INVERTED",
int(params["IS_IDATAIN_INVERTED"]))
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
tiledata = {}
pipdata = {}
ignpip = set()
tile_ports = {}
read_pip_data('pcie_int_interface_l.txt', pipdata, tile_ports)
read_pip_data('pcie_int_interface_r.txt', pipdata, tile_ports)
print("Loading tags from design.txt.")
with open("design.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
if not tile.startswith('PCIE_INT_INTERFACE'):
continue
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set()
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
for tile, pips_srcs_dsts in tiledata.items():
tile_type = pips_srcs_dsts["type"]
pips = pips_srcs_dsts["pips"]
for src, dst in pipdata[tile_type]:
if (src, dst) in ignpip:
pass
elif (src, dst) in pips:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
else:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
db_root = get_db_root()
part = get_part()
clock_column = ClockColumn(db_root, part)
segmk = Segmaker("design.bits")
print("Loading tags from design.txt.")
with open("route.txt", "r") as f:
for line in f:
if 'CLK_BUFG_REBUF' not in line:
continue
parts = line.replace('{', '').replace('}', '').strip().replace(
'\t', ' ').split(' ')
dst = parts[0]
pip = parts[3]
tile_from_pip, pip = pip.split('/')
if 'CLK_BUFG_REBUF' not in tile_from_pip:
continue
tile_type, pip = pip.split('.')
assert tile_type == 'CLK_BUFG_REBUF'
wire_a, wire_b = pip.split('<<->>')
tile_from_wire, dst = dst.split('/')
assert dst == wire_a
if tile_from_wire == tile_from_pip:
b_to_a = wire_a == dst
a_to_b = not b_to_a
else:
b_to_a = wire_a != dst
a_to_b = not b_to_a
segmk.add_tile_tag(
tile_from_pip, '{}.{}'.format(wire_a, wire_b), b_to_a)
segmk.add_tile_tag(
tile_from_pip, '{}.{}'.format(wire_b, wire_a), a_to_b)
clock_column.enable_rebuf(tile_from_pip, wire_a)
for tile, gclk, active_below, active_above in clock_column.yield_rebuf_state(
):
segmk.add_tile_tag(
tile, 'GCLK{}_ENABLE_ABOVE'.format(gclk), active_above)
segmk.add_tile_tag(
tile, 'GCLK{}_ENABLE_BELOW'.format(gclk), active_below)
segmk.compile()
segmk.write(allow_empty=True)
def run():
segmk = Segmaker("design.bits")
print("Loading tags")
f = open('params.jl', 'r')
f.readline()
for l in f:
j = json.loads(l)
bus_tags(segmk, j, j['site'])
segmk.compile(bitfilter=bitfilter)
segmk.write()
def run():
segmk = Segmaker("design.bits")
print("Loading tags")
f = open('params.jl', 'r')
f.readline()
for l in f:
j = json.loads(l)
ps = j['params']
assert j['module'] == 'my_PLLE2_ADV'
site = verilog.unquote(ps['LOC'])
bus_tags(segmk, ps, site)
segmk.compile()
segmk.write()
def main():
segmk = Segmaker("design.bits")
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
for tile_param in params:
for param, tag in (
('Y0_IN_USE', 'RAMB18_Y0.IN_USE'),
('Y1_IN_USE', 'RAMB18_Y1.IN_USE'),
('FIFO_Y0_IN_USE', 'RAMB18_Y0.FIFO_MODE'),
('FIFO_Y1_IN_USE', 'RAMB18_Y1.FIFO_MODE'),
):
segmk.add_tile_tag(tile_param['tile'], tag, tile_param[param])
segmk.compile(bitfilter=bitfilter)
segmk.write()
def run():
segmk = Segmaker("design.bits")
print("Loading params")
f = open("params.json")
params = json.load(f)
params = {p["site"]: p for p in params}
print("Loading tags")
f = open('params.jl', 'r')
f.readline()
for l in f:
j = json.loads(l)
bus_tags(segmk, j, params, j['site'])
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
for row in params:
base_name = 'BUFGCTRL_X{}Y{}'.format(row['x'], row['y'])
segmk.add_site_tag(row['site'], '{}.IN_USE'.format(base_name),
row['IN_USE'])
if not row['IN_USE']:
continue
for param in (
'INIT_OUT',
'IS_IGNORE0_INVERTED',
'IS_IGNORE1_INVERTED',
):
segmk.add_site_tag(row['site'], '{}.{}'.format(base_name, param),
row[param])
for param in ('PRESELECT_I0', ):
segmk.add_site_tag(row['site'], '{}.Z{}'.format(base_name, param),
1 ^ row[param])
for param in ('PRESELECT_I1', ):
segmk.add_site_tag(row['site'], '{}.{}'.format(base_name, param),
row[param])
for param, tag in (('IS_CE0_INVERTED', 'ZINV_CE0'), ('IS_S0_INVERTED',
'ZINV_S0'),
('IS_CE1_INVERTED', 'ZINV_CE1'), ('IS_S1_INVERTED',
'ZINV_S1')):
segmk.add_site_tag(row['site'], '{}.{}'.format(base_name, tag),
1 ^ row[param])
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
for tile_param in params:
if tile_param['BRAM36_IN_USE']:
write_ram_ext_tags(segmk, tile_param)
segmk.add_site_tag(tile_param['site'], 'BRAM36_IN_USE', 1)
segmk.add_site_tag(tile_param['site'], 'EN_ECC_READ',
tile_param['EN_ECC_READ'])
segmk.add_site_tag(tile_param['site'], 'EN_ECC_WRITE',
tile_param['EN_ECC_WRITE'])
else:
segmk.add_site_tag(tile_param['site'], 'BRAM36_IN_USE', 0)
segmk.compile()
segmk.write()
def run():
segmk = Segmaker("design.bits")
clk_inverts = {}
with open('design.csv', 'r') as f:
for params in csv.DictReader(f):
clk_inverts[params['site']] = params
print("Loading tags")
f = open('params.jl', 'r')
f.readline()
for l in f:
j = json.loads(l)
ps = j['params']
assert j['module'] == 'my_RAMB18E1'
site = verilog.unquote(ps['LOC'])
bus_tags(segmk, ps, site)
if ps['RAM_MODE'] == '"TDP"':
rw_width_tags(segmk, ps, site)
segmk.add_site_tag(
site, 'SDP_READ_WIDTH_36', ps['RAM_MODE'] == '"SDP"'
and int(ps['READ_WIDTH_A']) == 36)
segmk.add_site_tag(
site, 'SDP_WRITE_WIDTH_36', ps['RAM_MODE'] == '"SDP"'
and int(ps['WRITE_WIDTH_B']) == 36)
if ps['READ_WIDTH_A'] < 36 and ps['WRITE_WIDTH_B'] < 36:
isinv_tags(segmk, ps, site, clk_inverts[site])
write_mode_tags(segmk, ps, site)
write_rstreg_priority(segmk, ps, site)
write_rdaddr_collision(segmk, ps, site)
def bitfilter(frame, bit):
# rw_width_tags() aliasing interconnect on large widths
return frame not in (0, 20, 21)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
print("Loading tags")
with open('params.json') as f:
params = json.load(f)
for tile_param in params:
if tile_param['EN_SYN'] and tile_param['DATA_WIDTH'] == 4:
output_integer_tags(segmk,
tile_param,
'ALMOST_EMPTY_OFFSET',
invert=True)
output_integer_tags(segmk,
tile_param,
'ALMOST_FULL_OFFSET',
invert=True)
for param in ('EN_SYN', 'FIRST_WORD_FALL_THROUGH'):
segmk.add_tile_tag(tile_param['tile'], param, tile_param[param])
segmk.compile()
segmk.write()
def run():
segmk = Segmaker("design.bits")
print("Loading tags")
f = open('params.jl', 'r')
design = json.load(f)
for p in design:
ps = p["params"]
if p["site_type"] in "ICAP":
param = verilog.unquote(ps["ICAP_WIDTH"])
segmaker.add_site_group_zero(segmk, p["site"], "ICAP_WIDTH_",
["X32", "X8", "X16"], "X32", param)
elif p["site_type"] in "BSCAN":
param = str(ps["JTAG_CHAIN"])
segmaker.add_site_group_zero(segmk, p["site"], "JTAG_CHAIN_",
["1", "2", "3", "4"], param, param)
elif p["site_type"] in "CAPTURE":
param = verilog.unquote(ps["ONESHOT"])
segmk.add_site_tag(p["site"], "ONESHOT",
True if param in "TRUE" else False)
elif p["site_type"] in "STARTUP":
param = verilog.unquote(ps["PROG_USR"])
segmk.add_site_tag(p["site"], "PROG_USR",
True if param in "TRUE" else False)
elif p["site_type"] in "FRAME_ECC":
param = verilog.unquote(ps["FARSRC"])
segmaker.add_site_group_zero(segmk, p["site"], "FARSRC_",
["FAR", "EFAR"], param, param)
elif p["site_type"] in ["USR_ACCESS", "DCIRESET"]:
feature = "ENABLED"
segmk.add_site_tag(p["site"], feature,
True if ps["ENABLED"] else False)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
designdata = {}
tiledata = {}
pipdata = {}
ppipdata = {}
ignpip = set()
piplists = ['cmt_top_l_upper_t.txt', 'cmt_top_r_upper_t.txt']
ppiplists = ['ppips_cmt_top_l_upper_t.db', 'ppips_cmt_top_r_upper_t.db']
# Load PIP lists
print("Loading PIP lists...")
for piplist in piplists:
with open(
os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'cmt_top', piplist)) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
pipdata[tile_type].append((src, dst))
# Load PPIP lists (to exclude them)
print("Loading PPIP lists...")
for ppiplist in ppiplists:
fname = os.path.join(os.getenv('FUZDIR'), '..', '071-ppips', 'build',
ppiplist)
with open(fname, 'r') as f:
for l in f:
pip_data, pip_type = l.strip().split()
if pip_type != 'always':
continue
tile_type, dst, src = pip_data.split('.')
if tile_type not in ppipdata:
ppipdata[tile_type] = []
ppipdata[tile_type].append((src, dst))
# Load desgin data
print("Loading design data...")
with open("design.txt", "r") as f:
for line in f:
fields = line.strip().split(",")
designdata[fields[0]] = fields[1:]
with open("design_pips.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
if not tile.startswith('CMT_TOP'):
continue
if 'UPPER_B' in tile:
continue
if 'LOWER_T' in tile:
continue
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set(),
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
if dst.startswith('CMT_TOP_R_UPPER_T_CLK') or \
dst.startswith('CMT_TOP_L_UPPER_T_CLK'):
ignpip.add((src, dst))
tags = {}
# Populate IN_USE tags
for tile, (site, in_use) in designdata.items():
if tile not in tags:
tags[tile] = {}
tags[tile]["IN_USE"] = int(in_use)
# Populate PIPs
for tile in tags.keys():
tile_type = tile.rsplit("_", maxsplit=1)[0]
in_use = tags[tile]["IN_USE"]
internal_feedback = False
if not in_use:
active_pips = []
else:
active_pips = tiledata[tile]["pips"]
for src, dst in pipdata[tile_type]:
if (src, dst) in ignpip:
continue
if (src, dst) in ppipdata[tile_type]:
continue
tag = "{}.{}".format(dst, src)
val = in_use if (src, dst) in active_pips else False
if not (in_use and not val):
tags[tile][tag] = int(val)
# Output tags
for tile, tile_tags in tags.items():
for t, v in tile_tags.items():
segmk.add_tile_tag(tile, t, v)
segmk.compile(bitfilter=bitfilter)
segmk.write()
tiledata[tile] = {
"pips": set(),
"nodes": set(),
}
if ab == "A":
tiledata[tile]["pips"].add((dst, src))
pipdata.add((dst, src))
else:
tiledata[tile]["nodes"].add(src)
tiledata[tile]["nodes"].add(dst)
for tile, pips_nodes in tiledata.items():
pips = pips_nodes["pips"]
nodes = pips_nodes["nodes"]
for dst, src in pipdata:
if (dst, src) in pips:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
elif dst not in nodes and src not in nodes:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
def bitfilter(frame_idx, bit_idx):
assert os.getenv("XRAY_DATABASE") in ["artix7", "kintex7"]
return frame_idx in [0, 1]
segmk.compile(bitfilter=bitfilter)
segmk.write(allow_empty=True)
def main():
print("Loading tags")
segmk = Segmaker("design.bits")
'''
port,site,tile,pin,slew,drive,pulltype
di[0],IOB_X0Y107,LIOB33_X0Y107,A21,PULLDOWN
di[10],IOB_X0Y147,LIOB33_X0Y147,F14,PULLUP
'''
with open('params.jl', 'r') as f:
design = json.load(f)
for d in design:
site = d['site']
if skip_broken_tiles(d):
continue
iostandard = verilog.unquote(d['IOSTANDARD'])
stepdown = iostandard in STEPDOWN_IOSTANDARDS
segmk.add_site_tag(site, '_'.join(STEPDOWN_IOSTANDARDS), stepdown)
if d['type'] is None:
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
for drive in drives_for_iostandard(iostandard):
segmk.add_site_tag(
site,
'{}.DRIVE.I{}.IN_OUT_COMMON'.format(iostandard,
drive), 0)
elif d['type'] == 'IBUF':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
for drive in drives_for_iostandard(iostandard):
segmk.add_site_tag(
site,
'{}.DRIVE.I{}.IN_OUT_COMMON'.format(iostandard,
drive), 1)
elif d['type'] == 'OBUF':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
for drive in drives_for_iostandard(iostandard):
if drive == d['DRIVE']:
segmk.add_site_tag(
site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
iostandard, drive), 1)
else:
segmk.add_site_tag(
site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
iostandard, drive), 0)
elif d['type'] == 'IOBUF_INTERMDISABLE':
segmk.add_site_tag(site, 'INOUT', 1)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
if d['type'] is not None:
segmaker.add_site_group_zero(
segmk, site, "PULLTYPE.",
("NONE", "KEEPER", "PULLDOWN", "PULLUP"), "PULLDOWN",
verilog.unquote(d['PULLTYPE']))
if d['type'] == 'IBUF' or d['type'] is None:
continue
drive_opts = set()
for opt in ("LVCMOS25", "LVCMOS33", "LVCMOS18", "LVCMOS15",
"LVCMOS12", 'LVTTL'):
for drive_opt in ("4", "8", "12", "16", "24"):
if drive_opt == "16" and opt == "LVCMOS12":
continue
if drive_opt == "24" and opt not in ["LVCMOS18", 'LVTTL']:
continue
drive_opts.add(mk_drive_opt(opt, drive_opt))
segmaker.add_site_group_zero(segmk, site, '', drive_opts,
mk_drive_opt('LVCMOS25', '12'),
mk_drive_opt(iostandard, d['DRIVE']))
segmaker.add_site_group_zero(segmk, site, "SLEW.",
("SLOW", "FAST"), "FAST",
verilog.unquote(d['SLEW']))
if 'ibufdisable_wire' in d:
segmk.add_site_tag(site, 'IBUFDISABLE.I',
d['ibufdisable_wire'] != '0')
if 'intermdisable_wire' in d:
segmk.add_site_tag(site, 'INTERMDISABLE.I',
d['intermdisable_wire'] != '0')
segmk.compile(bitfilter=bitfilter)
segmk.write(allow_empty=True)
def run():
segmk = Segmaker("design.bits", verbose=True)
print("Loading tags")
with open('params.json', 'r') as fp:
data = json.load(fp)
used_dsps = set()
for params in data['instances']:
dsp = "DSP_0" if params['SITE'][-1] in "02468" else "DSP_1"
site = params['SITE']
if params['USE_DPORT'] == quote(
"TRUE") and params['USE_MULT'] != quote("NONE"):
add(segmk, site, dsp, 'ADREG', 0, to_int(params['ADREG']), 1)
add(segmk, site, dsp, 'ALUMODEREG', 0, to_int(params['ALUMODEREG']), 1)
if params['A_INPUT'] == quote("DIRECT"):
add(segmk, site, dsp, 'AREG_0', 0,
int(to_int(params['AREG']) == 0), 0, False)
add(segmk, site, dsp, 'AREG_2', 0,
int(to_int(params['AREG']) == 2), 0, False)
if params['B_INPUT'] == quote("DIRECT"):
add(segmk, site, dsp, 'BREG_0', 0,
int(to_int(params['BREG']) == 0), 0, False)
add(segmk, site, dsp, 'BREG_2', 0,
int(to_int(params['BREG']) == 2), 0, False)
if params['A_INPUT'] == quote("CASCADE"):
add(
segmk, site, dsp, 'AREG_2_ACASCREG_1', 0,
int(
to_int(params['AREG']) == 2
and to_int(params['ACASCREG']) == 1), 0, False)
add(
segmk, site, dsp, 'AREG_2_ACASCREG_1', 0,
int(
to_int(params['AREG']) == 2
and to_int(params['ACASCREG']) == 1), 1, False)
if params['B_INPUT'] == quote("CASCADE"):
add(
segmk, site, dsp, 'BREG_2_BCASCREG_1', 0,
int(
to_int(params['BREG']) == 2
and to_int(params['BCASCREG']) == 1), 0, False)
add(
segmk, site, dsp, 'BREG_2_BCASCREG_1', 0,
int(
to_int(params['BREG']) == 2
and to_int(params['BCASCREG']) == 1), 1, False)
add(segmk, site, dsp, 'CARRYINREG', 0, to_int(params['CARRYINREG']), 1)
add(segmk, site, dsp, 'CARRYINSELREG', 0,
to_int(params['CARRYINSELREG']), 1)
add(segmk, site, dsp, 'CREG', 0, to_int(params['CREG']), 1)
if params['USE_DPORT'] == quote(
"TRUE") and params['USE_MULT'] != quote("NONE"):
add(segmk, site, dsp, 'DREG', 0, to_int(params['DREG']), 1)
add(segmk, site, dsp, 'INMODEREG', 0, to_int(params['INMODEREG']), 1)
add(segmk, site, dsp, 'OPMODEREG', 0, to_int(params['OPMODEREG']), 1)
add(segmk, site, dsp, 'PREG', 0, to_int(params['PREG']), 1)
INPUT = {}
INPUT[quote('DIRECT')] = 0
INPUT[quote('CASCADE')] = 1
add(segmk, site, dsp, 'A_INPUT', 0, INPUT[params['A_INPUT']], 0)
add(segmk, site, dsp, 'B_INPUT', 0, INPUT[params['B_INPUT']], 0)
BOOL = {}
BOOL[quote('FALSE')] = 0
BOOL[quote('TRUE')] = 1
add(segmk, site, dsp, 'USE_DPORT', 0, BOOL[params['USE_DPORT']], 0)
add(segmk, site, dsp, 'USE_SIMD_FOUR12', 0,
params['USE_SIMD'] == quote("FOUR12"), 0, False)
add(segmk, site, dsp, 'USE_SIMD_FOUR12_TWO24', 0, params['USE_SIMD']
in (quote("TWO24"), quote("FOUR12")), 0, False)
MULT = {}
MULT[quote('NONE')] = 0
MULT[quote('MULTIPLY')] = 1
MULT[quote('DYNAMIC')] = 2
for i in range(2):
add(segmk, site, dsp, 'USE_MULT', i, MULT[params['USE_MULT']], 0)
add(segmk, site, dsp, 'MREG', 0, to_int(params['MREG']), 1)
AUTORESET = {}
AUTORESET[quote('NO_RESET')] = 0
AUTORESET[quote('RESET_NOT_MATCH')] = 1
AUTORESET[quote('RESET_MATCH')] = 2
add(segmk, site, dsp, 'AUTORESET_PATDET_RESET_NOT_MATCH', 0,
params['AUTORESET_PATDET'] == quote("RESET_NOT_MATCH"), 0, False)
add(
segmk, site, dsp, 'AUTORESET_PATDET_RESET', 0,
params['AUTORESET_PATDET']
in (quote("RESET_NOT_MATCH"), quote("RESET_MATCH")), 0, False)
for i in range(48):
add(segmk, site, dsp, 'MASK', i, to_int(params['MASK']), 0)
for i in range(48):
add(segmk, site, dsp, 'PATTERN', i, to_int(params['PATTERN']), 0)
if params['USE_PATTERN_DETECT'] == quote("PATDET"):
add_site_group_zero(segmk, site, dsp + ".", [
"SEL_MASK_%s" % x
for x in ["MASK", "C", "ROUNDING_MODE1", "ROUNDING_MODE2"]
], "SEL_MASK_MASK", "SEL_MASK_%s" % (params['SEL_MASK'][1:-1]))
USE_PATTERN_DETECT = {}
USE_PATTERN_DETECT[quote('NO_PATDET')] = 0
USE_PATTERN_DETECT[quote('PATDET')] = 1
add(segmk, site, dsp, 'USE_PATTERN_DETECT', 0,
USE_PATTERN_DETECT[params['USE_PATTERN_DETECT']], 0)
inv_ports = [
("ALUMODE", 4),
("CARRYIN", 1),
("CLK", 1),
("INMODE", 5),
("OPMODE", 7),
]
for port, width in inv_ports:
param = 'IS_{}_INVERTED'.format(port)
for i in range(width):
add(segmk, site, dsp, param, i, to_int(params[param]), 1,
width > 1)
segmk.compile()
segmk.write()
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
t = ("_".join(tile.split("_")[0:2]), dst, src)
if pnum == 1 or pdir == 0:
verbose and print('ignore pnum == 1 or pdir == 0: ', pip)
ignpip.add(t)
if t not in todo:
verbose and print('ignore not todo: ', t)
ignpip.add(t)
for tile, pips_srcs_dsts in tiledata.items():
pips = pips_srcs_dsts["pips"]
srcs = pips_srcs_dsts["srcs"]
dsts = pips_srcs_dsts["dsts"]
for (tile_lr, pip), src_dst in pipdata.items():
src, dst = src_dst
t = (tile_lr, dst, src)
if t in ignpip:
pass
elif pip in pips:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
elif src_dst[1] not in dsts:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
segmk.compile(bitfilter=get_bitfilter(os.getenv('XRAY_DATABASE'), 'INT'))
segmk.write()
# Can we find instance where they are not aliased?
WA7USED = 0
import sys, re, os
from prjxray.segmaker import Segmaker
segmk = Segmaker("design.bits")
print("Loading tags")
'''
module,loc,c31,b31,a31
my_NDI1MUX_NI_NMC31,SLICE_X12Y100,1,1,0
my_NDI1MUX_NI_NMC31,SLICE_X12Y101,1,1,1
my_NDI1MUX_NI_NMC31,SLICE_X12Y102,1,1,1
'''
f = open('params.csv', 'r')
f.readline()
for l in f:
l = l.strip()
module, loc, c31, b31, a31 = l.split(',')
c31 = int(c31)
b31 = int(b31)
a31 = int(a31)
segmk.add_site_tag(loc, "ADI1MUX.AI", 1 ^ a31)
segmk.add_site_tag(loc, "BDI1MUX.BI", 1 ^ b31)
segmk.add_site_tag(loc, "CDI1MUX.CI", 1 ^ c31)
segmk.compile()
segmk.write()
def main():
segmk = Segmaker("design.bits")
tiledata = {}
pipdata = {}
ignpip = set()
with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'clk_bufg', 'clk_bufg_bot_r.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
pipdata[tile_type].append((src, dst))
with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'clk_bufg', 'clk_bufg_top_r.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
pipdata[tile_type].append((src, dst))
print("Loading tags from design.txt.")
with open("design.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
if not tile.startswith('CLK_BUFG'):
continue
if tile.startswith('CLK_BUFG_REBUF'):
continue
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set()
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
muxed_src = re.match(
'^CLK_BUFG_(TOP|BOT)_R_CK_MUXED', src) is not None
if pnum == 1 or pdir == 0 or \
muxed_src:
ignpip.add((src, dst))
for tile, pips_srcs_dsts in tiledata.items():
tile_type = pips_srcs_dsts["type"]
pips = pips_srcs_dsts["pips"]
for src, dst in pipdata[tile_type]:
if (src, dst) in ignpip:
pass
elif (src, dst) in pips:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
elif dst not in tiledata[tile]["dsts"]:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
tiledata = {}
pipdata = {}
ignpip = set()
tile_ports = {}
with open(
os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'hclk_ioi3', 'hclk_ioi3.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
tile_ports[tile_type] = set()
pipdata[tile_type].append((src, dst))
tile_ports[tile_type].add(src)
tile_ports[tile_type].add(dst)
print("Loading tags from design.txt.")
with open("design.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
if not tile.startswith('HCLK_IOI3'):
continue
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set()
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
if "IDELAYCTRL" not in dst:
ignpip.add((src, dst))
for tile, pips_srcs_dsts in tiledata.items():
tile_type = pips_srcs_dsts["type"]
pips = pips_srcs_dsts["pips"]
for src, dst in pipdata[tile_type]:
if (src, dst) in ignpip:
pass
elif (src, dst) in pips:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
elif dst not in tiledata[tile]["dsts"]:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
segmk.compile(bitfilter=bitfilter)
segmk.write()
def main():
segmk = Segmaker("design.bits")
tiledata = {}
pipdata = {}
ignpip = set()
tile_ports = {}
with open(
os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'hclk_cmt', 'hclk_cmt.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
tile_ports[tile_type] = set()
pipdata[tile_type].append((src, dst))
tile_ports[tile_type].add(src)
tile_ports[tile_type].add(dst)
with open(
os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
'hclk_cmt', 'hclk_cmt_l.txt')) as f:
for l in f:
tile_type, dst, src = l.strip().split('.')
if tile_type not in pipdata:
pipdata[tile_type] = []
tile_ports[tile_type] = set()
pipdata[tile_type].append((src, dst))
tile_ports[tile_type].add(src)
tile_ports[tile_type].add(dst)
tile_to_cmt = {}
cmt_to_hclk_cmt = {}
with open(os.path.join(os.getenv('FUZDIR'), 'build',
'cmt_regions.csv')) as f:
for l in f:
site, cmt, tile = l.strip().split(',')
tile_to_cmt[tile] = cmt
if tile.startswith('HCLK_CMT'):
cmt_to_hclk_cmt[cmt] = tile
active_ioclks = set()
print("Loading tags from design.txt.")
with open("design.txt", "r") as f:
for line in f:
tile, pip, src, dst, pnum, pdir = line.split()
pip_prefix, _ = pip.split(".")
tile_from_pip, tile_type = pip_prefix.split('/')
assert tile == tile_from_pip
_, src = src.split("/")
_, dst = dst.split("/")
pnum = int(pnum)
pdir = int(pdir)
if src in IOCLK_MAP:
active_ioclks.add(
(cmt_to_hclk_cmt[tile_to_cmt[tile]], IOCLK_MAP[src]))
if not tile.startswith('HCLK_CMT'):
continue
if tile not in tiledata:
tiledata[tile] = {
"type": tile_type,
"pips": set(),
"srcs": set(),
"dsts": set()
}
tiledata[tile]["pips"].add((src, dst))
tiledata[tile]["srcs"].add(src)
tiledata[tile]["dsts"].add(dst)
if pdir == 0:
tiledata[tile]["srcs"].add(dst)
tiledata[tile]["dsts"].add(src)
if pnum == 1 or pdir == 0:
ignpip.add((src, dst))
for tile, pips_srcs_dsts in tiledata.items():
tile_type = pips_srcs_dsts["type"]
pips = pips_srcs_dsts["pips"]
for src, dst in pipdata[tile_type]:
if (src, dst) in ignpip:
pass
elif (src, dst) in pips:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
elif dst not in tiledata[tile]["dsts"]:
segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
for port in tile_ports[tile_type]:
# These ones do not have any outgoing connections from the tile.
if "FREQ_REF" in port:
continue
# There seems to be no special bits related to use of
# HCLK_CMT_MUX_CLKINT_n wires.
if "HCLK_CMT_MUX_CLKINT" in port:
continue
# It seems that CCIOn_USED is not enabled when a net goes through
# FREQ_REFn. Do not emit this tag if this happens.
if "CCIO" in port:
n = int(port[-1])
dst = "HCLK_CMT_MUX_OUT_FREQ_REF{}".format(n)
if dst in tiledata[tile]["dsts"]:
continue
if port in tiledata[tile]["dsts"] or port in tiledata[tile]["srcs"]:
segmk.add_tile_tag(tile, "{}_USED".format(port), 1)
else:
segmk.add_tile_tag(tile, "{}_USED".format(port), 0)
for ioclk in IOCLK_SRCS:
if ioclk in tiledata[tile]["srcs"] or (tile,
ioclk) in active_ioclks:
segmk.add_tile_tag(tile, "{}_ACTIVE".format(ioclk), 1)
else:
segmk.add_tile_tag(tile, "{}_ACTIVE".format(ioclk), 0)
segmk.compile(bitfilter=bitfilter)
segmk.write()
