def test():
filelist = [codedir + 'case.v']
topmodule = 'TOP'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist,
topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
output = []
output.append(list(binddict.values())[0][0].tostr())
output.append('\n')
rslt = ''.join(output)
print(rslt)
assert (expected == rslt)
def test():
filelist = [codedir + 'primitive.v']
topmodule = 'TOP'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist,
topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
output = []
for bk, bv in sorted(binddict.items(), key=lambda x: str(x[0])):
for bvi in bv:
output.append(bvi.tostr())
output.append('\n')
rslt = ''.join(output)
print(rslt)
assert (expected == rslt)
def test():
filelist = [codedir + 'supply.v']
topmodule = 'TOP'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist, topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
output = []
for bk, bv in sorted(binddict.items(), key=lambda x:str(x[0])):
for bvi in bv:
output.append(bvi.tostr())
output.append('\n')
rslt = ''.join(output)
print(rslt)
assert(expected == rslt)
def test():
filelist = [codedir + 'signed_task.v']
topmodule = 'TOP'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist, topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
output = []
output.append(list(binddict.values())[0][0].tostr())
output.append('\n')
rslt = ''.join(output)
print(rslt)
assert(expected == rslt)
def test():
filelist = [codedir + 'led.v']
topmodule = 'led'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist,
topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
output = []
output.append('Directive:\n')
for dr in sorted(directives, key=lambda x: str(x)):
output.append(str(dr))
output.append('\n')
output.append('Instance:\n')
for module, instname in sorted(instances, key=lambda x: str(x[1])):
output.append(str((module, instname)))
output.append('\n')
output.append('Term:\n')
for tk, tv in sorted(terms.items(), key=lambda x: str(x[0])):
output.append(tv.tostr())
output.append('\n')
output.append('Bind:\n')
for bk, bv in sorted(binddict.items(), key=lambda x: str(x[0])):
for bvi in bv:
output.append(bvi.tostr())
output.append('\n')
rslt = ''.join(output)
print(rslt)
assert (expected == rslt)
def test():
filelist = [codedir + 'blocking.v']
topmodule = 'TOP'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist, topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
output = []
output.append('Directive:\n')
for dr in sorted(directives, key=lambda x:str(x)):
output.append(str(dr))
output.append('\n')
output.append('Instance:\n')
for module, instname in sorted(instances, key=lambda x:str(x[1])):
output.append(str((module, instname)))
output.append('\n')
output.append('Term:\n')
for tk, tv in sorted(terms.items(), key=lambda x:str(x[0])):
output.append(tv.tostr())
output.append('\n')
output.append('Bind:\n')
for bk, bv in sorted(binddict.items(), key=lambda x:str(x[0])):
for bvi in bv:
output.append(bvi.tostr())
output.append('\n')
rslt = ''.join(output)
print(rslt)
assert(expected == rslt)
def test():
filelist = [codedir + 'partselect_assign.v']
topmodule = 'TOP'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist,
topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
c_analyzer = VerilogControlflowAnalyzer(
topmodule,
terms,
binddict,
resolved_terms=optimizer.getResolvedTerms(),
resolved_binddict=optimizer.getResolvedBinddict(),
constlist=optimizer.getConstlist())
output = []
for tk in sorted(c_analyzer.resolved_terms.keys(), key=lambda x: str(x)):
tree = c_analyzer.makeTree(tk)
output.append(str(tk) + ': ' + tree.tocode())
rslt = '\n'.join(output) + '\n'
print(rslt)
assert (expected == rslt)
def test():
filelist = [codedir + 'partselect_assign.v']
topmodule = 'TOP'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist, topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
c_analyzer = VerilogControlflowAnalyzer(topmodule, terms,
binddict,
resolved_terms=optimizer.getResolvedTerms(),
resolved_binddict=optimizer.getResolvedBinddict(),
constlist=optimizer.getConstlist()
)
output = []
for tk in sorted(c_analyzer.resolved_terms.keys(), key=lambda x:str(x)):
tree = c_analyzer.makeTree(tk)
output.append(str(tk) + ': ' + tree.tocode())
rslt = '\n'.join(output) + '\n'
print(rslt)
assert(expected == rslt)
def test():
filelist = [codedir + 'reset.v']
topmodule = 'TOP'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist,
topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
sens_info = []
for tk in sorted(binddict.keys(), key=lambda x: str(x)):
sens_info.append(str(tk) + ': ')
reset_info = (str(binddict[tk][0].getResetEdge()) + ' ' +
str(binddict[tk][0].getResetName()) + '[' +
str(binddict[tk][0].getResetBit()) + ']')
clock_info = (str(binddict[tk][0].getClockEdge()) + ' ' +
str(binddict[tk][0].getClockName()) + '[' +
str(binddict[tk][0].getClockBit()) + ']')
sens_info.append(reset_info + clock_info)
sens_info.append('\n')
rslt = ''.join(sens_info)
print(rslt)
assert (expected == rslt)
def main():
INFO = "Verilog module signal/module dataflow analyzer"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_dataflow_analyzer.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v",
"--version",
action="store_true",
dest="showversion",
default=False,
help="Show the version")
optparser.add_option("-I",
"--include",
dest="include",
action="append",
default=[],
help="Include path")
optparser.add_option("-D",
dest="define",
action="append",
default=[],
help="Macro Definition")
optparser.add_option("-t",
"--top",
dest="topmodule",
default="TOP",
help="Top module, Default=TOP")
optparser.add_option("--nobind",
action="store_true",
dest="nobind",
default=False,
help="No binding traversal, Default=False")
optparser.add_option(
"--noreorder",
action="store_true",
dest="noreorder",
default=False,
help="No reordering of binding dataflow, Default=False")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist,
options.topmodule,
noreorder=options.noreorder,
nobind=options.nobind,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
print('Directive:')
for dr in sorted(directives, key=lambda x: str(x)):
print(dr)
instances = analyzer.getInstances()
print('Instance:')
for module, instname in sorted(instances, key=lambda x: str(x[1])):
print((module, instname))
if options.nobind:
print('Signal:')
signals = analyzer.getSignals()
for sig in signals:
print(sig)
print('Const:')
consts = analyzer.getConsts()
for con in consts:
print(con)
else:
terms = analyzer.getTerms()
print('Term:')
for tk, tv in sorted(terms.items(), key=lambda x: str(x[0])):
print(tv.tostr())
binddict = analyzer.getBinddict()
print('Bind:')
for bk, bv in sorted(binddict.items(), key=lambda x: str(x[0])):
for bvi in bv:
print(bvi.tostr())
def main():
INFO = "Verilog module signal/module dataflow analyzer"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_dataflow_analyzer.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-I","--include",dest="include",action="append",
default=[],help="Include path")
optparser.add_option("-D",dest="define",action="append",
default=[],help="Macro Definition")
optparser.add_option("-t","--top",dest="topmodule",
default="TOP",help="Top module, Default=TOP")
optparser.add_option("--nobind",action="store_true",dest="nobind",
default=False,help="No binding traversal, Default=False")
optparser.add_option("--noreorder",action="store_true",dest="noreorder",
default=False,help="No reordering of binding dataflow, Default=False")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule,
noreorder=options.noreorder,
nobind=options.nobind,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
print('Directive:')
for dr in sorted(directives, key=lambda x:str(x)):
print(dr)
instances = analyzer.getInstances()
print('Instance:')
for module, instname in sorted(instances, key=lambda x:str(x[1])):
print((module, instname))
if options.nobind:
print('Signal:')
signals = analyzer.getSignals()
for sig in signals:
print(sig)
print('Const:')
consts = analyzer.getConsts()
for con in consts:
print(con)
else:
terms = analyzer.getTerms()
print('Term:')
for tk, tv in sorted(terms.items(), key=lambda x:str(x[0])):
print(tv.tostr())
binddict = analyzer.getBinddict()
print('Bind:')
for bk, bv in sorted(binddict.items(), key=lambda x:str(x[0])):
for bvi in bv:
print(bvi.tostr())
